Aggregated Renewal Markov Processes With Applications in Simulating Mobile Broadcast Systems

For purposes of simulating contemporary communication systems, it is, in many cases, useful to apply error models for specific levels of abstraction. Such models should approximate the packet error behavior of a given system at a specific protocol layer, thus incorporating the possible detrimental effects of lower protocol layers. Packet error models can efficiently be realized using finite-state models; for example, there exists a wide range of studies on using Markov models to simulate communication channels. In this paper, we consider aggregated Markov processes, which are a subclass of hidden Markov models (HMMs). Artificial limitations are set on the state transition probabilities of the models to find efficient methods of parameter estimation. We apply these models to the simulation of the performance of digital video broadcasting-handheld (DVB-H). The parameters of the packet error models are approximated as functions of the time-variant received signal strength and speed of a mobile vehicular DVB-H receiver, and it is shown that useful results may be achieved with the described packet error models, particularly when simulating mobile reception in field conditions.     

A ranked order filter implementation for parallel analog processing

Order statistic filtering, the generalization of which is ranked order filtering, is needed for many image-processing functions including median filtering and mathematical morphology. Combining order statistic functionality with the parallel operation and local connectivity of array processing approaches such as the cellular nonlinear network model, has the potential for very high performance in image processing. This paper examines the implementation of programmable ranked order extraction with a very compact hardware realization of an analog current-mode ranked order filter. The considerable savings in the required circuit area, compared to other circuits, make it possible to use the structure as a building block in a massively parallel signal processing array. The operation of the circuit is analyzed in detail with the help of simulations and measurement results obtained from a test chip manufactured in a 0.18-/spl mu/m standard digital CMOS technology are also presented. The simulations and measurement results verify the correct operation of the circuit and show that it is very suitable for inclusion in every cell of a large parallel processor array. This makes many grayscale processing functions available with truly parallel operation and therefore very high performance.