Refinement of the Subthreshold Slope Modeling for Advanced Bulk CMOS Devices

We present here a simple analytical model of the subthreshold slope of CMOS devices that successfully describes the long-channel plateau, the initial improvement for medium gate lengths, and the final degradation for short gate lengths. The model is based on the voltage-doping transformation (VDT) that leads to a new term in the subthreshold slope expression, explaining the degradation of the slope at very short channels. The potential minimum at the virtual cathode was expressed using a semiempirical expression that allows our model to fit to data that were extracted from simulation in a wide range of device parameters. Finally, the new slope model successfully reproduced experimental data that were measured on devices based on 90- and 65-nm technologies, demonstrating the validity of our model for advanced bulk CMOS technologies.     

The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?

This paper presents a general study on the germanium (Ge) condensation technique to assess its potential, issues and applications for advanced metal oxide semiconductor field effect transistor (MOSFET) technologies. The interest in such process for fabrication of ultrathin germanium on insulator (GeOI) layers for fully depleted GeOI MOSFETs application is first described. We highlight the impact of initial silicon on insulator (SOI) substrates uniformity on the process, determined as the key parameter to be improved. Next, a global procedure is described for MOSFETs integration on Ge layers grown on 75% Ge-enriched silicon germanium on insulator (SGOI) substrates obtained by the Ge condensation technique. A third section reviews the different local Ge condensation techniques for fabrication of SOI–GeOI hybrid substrates. Interests of such substrates for SOI–GeOI planar co-integration either at the microprocessor, at the cell or at the transistor level will be discussed. Finally, the fabrication of a first 50-nm-thick SOI–GeOI hybrid substrate is described.     

Investigation of a Sequential Three-Dimensional Process for Back-Illuminated CMOS Image Sensors With Miniaturized Pixels

A new 3-D CMOS image sensor architecture is presented as a potential candidate for submicrometer pixels. To overcome the scaling challenge related to miniaturized pixel design rules, far beyond traditional 3-D stacking alignment capabilities, a sequential construction is applied. This paper gives a technical overview of this 3-D scheme and validates a part of its building blocks. As a consequence of a sequential process, the thermal budget is limited to ensure bottom device immunity. Subsequently, high-quality SOI film transfer above the first layer by direct bonding and etch back is demonstrated. Finally, the low-temperature processing of HfO₂/TiN fully depleted silicon-on-insulator readout transistors is detailed and evaluated from a low frequency noise point of view.     

High threshold voltage matching performance on gate-all-around MOSFET

For the first time, threshold voltage matching was measured on multiple gate transistors, and particularly on Gate-All-Around transistors (GAA) with both doped and undoped channels. Good matching performance is demonstrated on doped channel transistors, thanks to the absence of pocket nor halo implants. But most of all, it is shown that suppressing the channel doping allows to drastically reduce the dopant induced fluctuations contribution and provides an A_Vt parameter as low as 1.4 mV μm, which is one of the best reported result on MOS transistors.     

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

The paradigm and the usage of CMOS are changing, and so are the requirements at all levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and density of integration, are subject to other prerogatives related to variability, manufacturability, power consumption/dissipation (mobile products!), mix of varied digital and analog/RF functions (system-on-chip integration), etc. Controllability of variations and static leakage will add to, and in certain products prevail, over speed and density. Implications at all levels are multiple and are more diverse than just speed and smallness. The goal of the authors has been to see the problem globally from the product level and to place its components in their true proportions. Therefore, we will start with drawing the product-level picture and placing it in a historical perspective. Next, we will review the state of the art, the requirements, and solutions at the level of materials, transistor, and technology. Detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented in this paper.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Integration of PtSi in p-Type MOSFETs Using a Sacrificial Low-Temperature Germanidation Process

In this letter, an original selective etching method of Pt with respect to PtSi using a sacrificial low-temperature germanidation process is used for the integration of valence band edge contacts in p-type MOSFET devices. After silicidation annealing, the excess of Pt due to incomplete reaction with silicon or standing on insulating layers can be transformed into the PtGe₂ phase. The solubility of this phase in a sulfuric peroxide mixture (SPM) without altering PtSi is demonstrated. The suitability and scalability of the proposed integration scheme is shown through the successful integration and characterization of PtSi source/drain contacts in p-type MOSFETs.