A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $SigmaDelta$ ADC Based on a Time Encoding Quantizer in 0.13 $mu$ m CMOS

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2^ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm².     

A one-path subsampling quadrature receiver based on a ΣΔ modulator with distributed resonators

This article presents experimental results of a quadrature bandpass sigma–delta (ΣΔ) modulator based on distributed resonators. The modulator employs transmission lines and transconductors as main components and does not require switches in the loop filter as in the case of switched-capacitor (discrete-time) filters. In addition, the proposed complex modulator does not require a quadrature mixer in the receiver. As main feature, the modulator architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The one-bit second-order modulator ADC is able to convert IF signals at fs/2 and 3fs/2 (fs = 50 MHz), achieving an ENOB = 10 bits within a 1 MHz signal bandwidth. Therefore the modulator may be feasible for the typical IF frequencies used in cellular base stations. Furthermore, it provides an image rejection grater than 70 dB. The 0.35 μm BiCMOS chip consumes 28 mW at 3.3 V supply voltage.     

Linear processing of PWM signals using a RC time encoded integrator

This paper describes a delay-and-addition cell that enables direct signal processing of pulse with modulation (PWM) encoded signals. The cell can be considered functionally equivalent to a switched capacitor integrator. However, both its input and output are synchronous PWM signals. As a difference to a switched capacitor integrator, the circuit does not require operational amplifiers and is composed of passive RC circuits, switches, comparators and digital logic. Circuit implementation non idealities such as offset and propagation delays have also been analyzed. The main advantage of this circuit is the possibility to operate at a low voltage. The paper shows measurements of a demonstration circuit implementing a first order filter. As an application example, the filter is used to attenuate the quantization noise of a sigma-delta signal, delivering a continuously varying PWM waveform from a synchronous bitstream.     

Continuous time sigma-delta modulator based on binary weighted charge balance

A novel multibit continuous time sigma-delta modulator architecture that does not require a flash converter is presented. The quantiser of this modulator is similar to an integrating ADC that is operated with a binary weighted charge balancing algorithm. The charge residue in the integrating ADC at the end of each conversion cycle is accumulated for the next conversion, providing first-order noise shaping. The modulator order can be increased by the addition of more integrating stages.     

A Subsampling Quadrature Σ∆ Modulator Based on Distributed Resonators for Use in Radio Receiver

The receiver architecture proposed in this brief seizes the subsampling properties of continuous-time sigma-delta (SigmaDelta) modulators based on distributed resonators to construct a quadrature receiver. The proposed architecture is based on a low-pass SigmaDelta modulator that subsamples an intermediate frequency signal around the sampling frequency and does not require quadrature mixers. Instead, the quadrature mixing is replaced by suitably choosing the sampling instants inside the loop. Two practical circuit implementations are proposed. The first one uses separate circuitry for the I and Q paths. The second architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The proposed modulator may be feasible for the typical IF frequencies used in cellular base stations.     

Design and implementation of a band-pass sigma delta modulator with distributed resonators

Continuous time band-pass sigma delta converters require the realization of high frequency resonators, which have been usually implemented with g _m-C or LC circuits. However, transmission lines have been for a long time a standard way to implement high Q resonators in RF circuits. Recently, some continuous-time sigma–delta (SD) modulator architectures using transmission lines have been proposed. Theoretical analyses have shown that this kind of architectures share some of the properties of both continuous-time (CT) and discrete-time (DT) modulators. On the other hand they have specific implementation problems which are not present in other modulator architectures. This paper makes a brief review of the particularities of these modulators and shows the experimental results of a band-pass modulator implemented in BiCMOS technology. As an advantage compared to standard continuous time designs, this modulator can be operated as a subsampling ADC, displays a better immunity to clock jitter and is tolerant to loop delay.     

Sixth-order programmable bandwidth bandpass sigma-delta modulator implemented with transmission lines

An implementation of a sixth-order bandpass continuous time sigma-delta modulator using transmission lines is presented. A single tuning coefficient allows the exchange of resolution and bandwidth in this modulator, owing to the use of a two path transformation that exploits the similarity between transmission line modulators and discrete time modulators. The modulator tolerates two clock cycles of excess loop delay and a high clock jitter.