Silicon-on-nothing MOSFETs: performance, short-channel effects, and backgate coupling

Silicon-on-nothing (SON) transistors with gate length varying from 0.25 /spl mu/m down to 80 nm exhibit excellent performance and scalability. The silicon-on-insulator (SOI)-like architecture with thin fully depleted Si film and ultrathin buried oxide results in attenuated short-channel effects (charge sharing, DIBL and fringing fields), high current, and electron mobility. A new model accounts for the intrinsic mechanisms of operation in SON MOSFETs: i) substrate depletion governed by source and drain via doping modulation, ii) relatively low coupling between the front- and backgates, iii) role of ultrathin buried oxide. The proposed model reproduces the variations of the threshold voltage and subthreshold swing and is useful for further device optimization.     

Reduced floating body effects in narrow channel SOI MOSFETs

An experimental demonstration is given of the reduction of floating body effects in narrow channel SOI MOSFETs, as manifested by the saturation region subthreshold characteristics, latch-up, and breakdown voltage. The mechanisms responsible for this reduction are explained by original experiments and simulations. These are a deterioration of the carrier lifetime near the channel edges caused by local stress and defects, and a lowering of the source-body built-in potential barrier, resulting from dopant outdiffusion/segregation into the isolation oxide     

Correct biasing rules for virtual DG mode operation in SOI-MOSFETs

The appropriate biasing rules for virtual double-gate (DG) operation of silicon-on-insulator (SOI)-MOSFETs are investigated. The cause for the optimistic subthreshold swing, achieved by the conventional biasing rule, is discussed and a correct methodology is proposed. Furthermore, we select the proper threshold voltages for the virtual DG operation based on the condition that both interfaces are simultaneously inverted.