Design and performance of a product code turbo encoding-decoding prototype

This paper presents the latest results on a block turbo decoder design. We propose a block turbo decoder circuit for the error protection of small data blocks such asAtm cells on anAwgn (additive white Gaussian noise) channel with a code rate close to 0.5. A prototype was developed atEnst Bretagne. It allowsBer (bit error rate) measurements down to 10^?9 and uses programmable gate arrays (Fpga Xilinx circuits). The elementary extendedBch code and the data block size can be modified to fit specifications of different applications.     

Low-Complexity High-Rate Reed--Solomon Block Turbo Codes

This letter considers high-rate block turbo codes (BTC) obtained by concatenation of two single-error-correcting Reed-Solomon (RS) constituent codes. Simulation results show that these codes perform within 1 dB of the theoretical limit for binary transmission over additive white Gaussian noise with a low-complexity decoder. A comparison with Bose-Chaudhuri-Hocquenghem BTCs of similar code rate reveals that RS BTCs have interesting advantages in terms of memory size and decoder complexity for very-high-data-rate decoding architectures.     

Performance of hybrid turbo codes

The authors present the latest results on turbo codes which are built from a serial concatenation between a block code (BCH) and a recursive systematic convolutional code. The performance on a Gaussian channel with QPSK modulation is evaluated     

Noise parameters for design of MMIC HEMT LNA

The letter gives the noise parameters of MOVPE HEMTs or the design of MMIC HEMT low-noise amplifiers. An example of the design of an HEMT LNA is given using these parameters. The MMIC LNA has been fabricated and exhibits a 2.3+or-0.2 dB noise figure with an associated gain of 12+or-2 dB in the 12-16 GHz frequency range. The measured performance is within 0.5 dB of the simulation.<>