排序方式: 共有25条查询结果,搜索用时 312 毫秒
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M Souquet T Restle R Krebs SF Le Grice RS Goody BM W?hrl 《Canadian Metallurgical Quarterly》1998,37(35):12144-12152
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Verdonckt-Vandebroek S. Crabbe E.F. Meyerson B.S. Harame D.L. Restle P.J. Stork J.M.C. Megdanis A.C. Stanis C.L. Bright A.A. Kroesen G.M.W. Warren A.C. 《Electron Device Letters, IEEE》1991,12(8):447-449
A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n+ polysilicon gate, and p+ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm2/V-s at 300 K and 980 cm2/V-s at 82 K were achieved in functional submicrometer p-MOSFETs 相似文献
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Chappell B.A. Chappell T.I. Schuster S.E. Segmuller H.M. Allan J.W. Franch R.L. Restle P.J. 《Solid-State Circuits, IEEE Journal of》1988,23(1):59-67
CMOS emitter-coupled logic (ECL) receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1-μm technology. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differential mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying assumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process 相似文献
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Xuejue Huang Restle P. Bucelot T. Yu Cao Tsu-Jae King Chenming Hu 《Solid-State Circuits, IEEE Journal of》2003,38(3):457-463
A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed. 相似文献
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The time to solve a multiple-stage problem is the sum of the times consumed by separate stages. If each stage is a random all-or-none process, then time to complete a stage is an exponentially distributed random variable, and time to complete the problem will have a gamma distribution (under suitable simplifying assumptions). From this theory, the number of stages in a problem can be estimated and goodness-of-fit tested. Results on 3 word puzzles, administered to 178 individual college students, agreed with theory, and the estimates of number of stages in each problem agreed well with independent judgments of number of stages. The same problems also were administered to groups of 4 Ss. The data suggest that all Ss progress at their usual pace toward solution, except that an S who made a mistake in interpreting the problem consumes and wastes his share of the group's time. This result agrees with the additional observation that the apparent social structure of the groups, as determined from analysis of sociometric choices, was equalitarian. (18 ref.) (PsycINFO Database Record (c) 2010 APA, all rights reserved) 相似文献
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Taur Y. Zicherman D.S. Lombardi D.R. Restle P.J. Hsu C.H. Nanafi H.I. Wordeman M.R. Davari B. Shahidi G.G. 《Electron Device Letters, IEEE》1992,13(5):267-269
A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results. It is shown to yield more accurate and consistent channel lengths for deep-submicrometer CMOS devices at room and low temperatures. It is also found that, for both nFET and pFET, the source-drain resistance is essentially independent of temperature from 300 to 77 K 相似文献
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Munishikha Kalia Sarah Willkomm Jens Christian Claussen Tobias Restle Alexandre M. J. J. Bonvin 《International journal of molecular sciences》2016,17(1)
The human Argonaute 2 (hAgo2) protein is a key player of RNA interference (RNAi). Upon complex formation with small non-coding RNAs, the protein initially interacts with the 5′-end of a given guide RNA through multiple interactions within the MID domain. This interaction has been reported to show a strong bias for U and A over C and G at the 5′-position. Performing molecular dynamics simulations of binary hAgo2/OH–guide–RNA complexes, we show that hAgo2 is a highly flexible protein capable of binding to guide strands with all four possible 5′-bases. Especially, in the case of C and G this is associated with rather large individual conformational rearrangements affecting the MID, PAZ and even the N-terminal domains to different degrees. Moreover, a 5′-G induces domain motions in the protein, which trigger a previously unreported interaction between the 5′-base and the L2 linker domain. Combining our in silico analyses with biochemical studies of recombinant hAgo2, we find that, contrary to previous observations, hAgo2 is capable of functionally accommodating guide strands regardless of the 5′-base. 相似文献