Performance and reliability enhancement for CVD tungsten polycidedCMOS transistors due to fluorine incorporation in the gate oxide

The impacts of CVD tungsten polycide (WSi_x) on MOSFET performance and reliability are studied in this letter. The WSi_x process is shown to enhance the S/D lateral extent for both N- and P-channel devices via C_GD and L_eff measurements, confirming previous suspicion. This enhanced S/D extent is found to be easily modulated by drain-to-gate bias, which is favorable for achieving both higher drive currents and higher S/D punch-through voltages than those of non-WSi_x devices. Both electron and hole mobility for the WSi_x device are also slightly higher and closer to the published data compared to the non-WSi_x case. These effects together yield about >5% improvement for nMOSFET and >10% improvement for pMOSFET in drive current at a given punch-through voltage. The channel hot-electron lifetime for the n-channel WSi_x device is about 10 times higher than that of the non-WSi_x one. These enhancements in both performance and reliability make the WSi_x device very attractive fog VLSI CMOS technologies     

Increased resistance in p-type poly-Si resistors by thermal annealreduction interface charge

The effect of thermal annealing on characteristics of p-type poly-Si thin-film resistors was investigated. A significant increase was observed as the source/drain anneal temperature or anneal time was increased. The increased resistance is due to a reduction in current component arising from field-enhanced current via grain-boundary trap states at the drain end of the resistor. The reduction is this field-enhanced current arises primarily from a reduction of positive charge density at the top and bottom oxide/poly-Si interfaces of the thin-film resistor (and thus a reduction in the magnitude of the drain electric field) with increased annealing temperature and time     

Modeling of nonhyperbolic sine I-Vcharacteristics in poly-Si resistors

Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I-V characteristic at low V_DS and an activation energy which is not simply decreasing monotonically with increasing V_DS. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent model which includes the effects of a reverse-biased diode at the drain end is presented. Numerical simulation results show excellent agreement with experiment in regard to the shape of the I -V characteristic and of the effective activation energy as a function of V_DS     

Rapid thermal hydrogen passivation of polysilicon MOSFETs

The effectiveness of rapid thermal annealing as a passivation technique using Si₃N₄ as a solid source of H is discussed. Polysilicon MOSFETs with an on/off ratio of 10⁷ can be obtained through rapid thermal hydrogen passivation, compared to an on/off ratio of 10⁶ after furnace passivation. The improvement of subthreshold slope, threshold voltage, and channel transconductance compared to unpassivated MOSFETs is greater for rapid thermal annealing (RTA) than for furnace passivation     

Leakage-current-induced hot-carrier degradation of p-channelMOSFETs

Leakage-current-induced hot-carrier effects have been observed during stressing of p-channel MOSFETs in the OFF state with V _GS>0 V and V_DS<0 V. This mode of stressing results in increased leakage current and a positive shift in the value of V_GS, corresponding to the onset of avalanche breakdown of the drain junction. These effects are related to generation of interface states near the drain in forward-mode operation. By comparison, conventional stressing in the ON state with V _GS<0 V and V_DS<0 V resulted in little change in these p-channel MOSFET characteristics     

Effects of channel width and parasitic bipolar action on p-typepoly-Si resistor characteristics

The effects of channel width on I-V characteristics of thin-film p-type poly-Si resistors are discussed, in particular for the case in which the resistor current is mainly due to field-enhanced generation of carriers at the drain end (as can be common at high drain electric field). A significant decrease in current per unit width (microamperes per micrometer) is observed as the channel width is reduced from 3 to 0.6 μm. This decrease in current per unit width is due to the influence of fixed positive charge along the channel edges, which decreases the beta value associated with parasitic bipolar action in this regime of device operation     

Scaled CMOS technologies with low sheet resistance at 0.06-μmgate lengths

A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-μm gate lengths (mean=5.2 Ω/sq, max=5.7 Ω/sq at 0.07 μm; mean=6.7 Ω/sq, max=8.1 Ω/sq at 0.06 μm, TiSi₂ thickness on S/D=38 nm), in contrast with previous Ti salicide processes which failed below 0.10 μm. The process was successfully implemented into a 1.5 V, 0.12-μm CMOS technology achieving excellent drive currents (723 and 312 μA/μm at I_OFF=1 nA/μm for nMOS and pMOS, respectively)     

Raised source/drain MOSFET with dual sidewall spacers

A raised source/drain (S/D) MOSFET with sidewall spacers formed both before and after selective epitaxial silicon deposition in S/D regions is discussed. The second spacer overlies any faceted regions of the epitaxial silicon near the gate edge and has advantages for MOSFETs with implant-doped or in-situ doped epitaxial silicon regions. In particular, the spacer can prevent S/D dopants from being implanted through any thinner faceted regions near the gate edge, which would otherwise result in a deeper than desired junction depth in the silicon substrate. Additionally, the spacer can prevent source-to-substrate salicide shorts through the thinner faceted regions     

A transistor performance figure-of-merit including the effect ofgate resistance and its application to scaling to sub-0.25-μm CMOSlogic technologies

This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25-μm CMOS process. A furnace TiSi₂ process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet resistance requirement is derived from the new FOM. Using this expression, requirements on the gate sheet resistance are calculated corresponding to a technology roadmap for performance and oxide thickness     

On/off current ratio in P-channel poly-Si MOSFETs: dependence onhot-carrier stress conditions

Stress effects on poly-Si PMOS devices are investigated, and stress is related to the improvement or degradation of PMOS on/off current ratio. P-channel polysilicon MOSFETs have been stressed in the saturation and off-state regimes. Both the drive (on) current and leakage (off) current can be either increased or decreased after particular bias stress. On/off current ratio can be decreased by a factor of 2 for a stress bias of V_GS=V_DS=-11 V, but can be increased by a factor of 50 for a stress bias of V_GS=-2 V, V_DS=-11 V. Two effects of bias stress have been identified in poly-Si PMOS devices for which the on/off current ratio can either be increased or decreased after stress bias depending on the value of stress bias V_GS. These effects of room-temperature stress are proposed to be due to either trapping of hot electrons or hot-hole-induced donor-type interface state generation