A charge-trapping-based technique to design low-voltage BiCMOSlogic circuits

New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits' performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-μm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates     

1.5 V high-speed electrostatic discharge free BiCMOS digitalcircuit

A novel circuit design that effectively eliminates the need for input protection circuits is described. Besides having an excellent electrostatic discharge (ESD) robustness, the simulation results have shown that this design outperforms current BiCMOS circuits in terms of speed, power, crossover capacitance, and chip area for a wide range of load capacitances, power supply voltages and technologies. The proposed circuit remains functional after an ESD test     

Analytical and numerical analyses of the delay time of BiCMOSstructures

Analytical expressions for the transient response of BiCMOS structures have been derived. The analysis is performed on conventional structures and structures employing short-channel MOSFETs. The equations relate the delay time to key device and technology parameters. In deriving the time response, the two basic conduction regions (linear and saturation) for the MOSFET have been considered. A numerical algorithm for solving for the delay time of BiCMOS structures taking into account high-level injection effects, base resistance, doping-dependent mobilities, and bandgap narrowing is presented. A figure of merit for the speed is derived and scaling the supply voltage is considered     

A redundant-binary partial-product generator based on a five-bit recoding technique

This paper describes a redundant-binary partial-product generator (RB PPG) that is based on a five-bit recoding technique, designed to operate in a 16 × 16-bit RB parallel multiplier. It produces only half the number of partial-products generated by a conventional modified Booth's algorithm (MBA) PPG, thus leading to significantly lower circuit complexity and better speed performance for the partial-product addition circuitry that generates the final output. Unlike other five-bit recoding PPGs suggested so far, the proposed PPG does not require any additional adders to generate the non-power-of-two multiples of the multiplicand. Circuit simulations have also shown that the proposed PPG has lower power dissipation when compared to other MBA PPGs, with only a slight disadvantage in speed. As a result, the benefits gained within the partial-product addition circuitry are not compromised.     

A temperature-dependent DC model for quarter-micron LDD pMOSFET'soperating in a Bi-MOS structure

A temperature-dependent analytical model for deep submicrometer LDD p-channel devices operating in a Bi-MOS structure is reported for the first time. This model is based on experimental data obtained from 0.25-μm process wafers with a wide range of technologies (0.25-1.0 μm). The measurements have been performed within the temperature range 223-398 K (-50°C to +125°C). The model accounts for the effects of independently biasing the source, drain, gate and body potentials, scaling, and the influence of temperature on the threshold voltage and the device currents. The effect of temperature on the device transconductance and the output conductance have also been examined. The results revealed that close agreement between the analytical model and the experimental has been achieved. Comparisons between the principal MOS current and the lateral bipolar current have been made to demonstrate the improvement of the latter with temperature for the quarter-micron devices     

A low-power 16×16-b parallel multiplier utilizingpass-transistor logic

This paper describes a low-power 16×16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8 μm double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz     

Schottky merged BiCMOS structures

A new merged BiCMOS structure is presented. It incorporates a Schottky diode between the base and the collector of the n-p-n bipolar transistor. The structure offers the same reduced area advantage of merged over conventional BiCMOS, and is shown to have granted latchup immunity to BiCMOS circuits. The device simulations using HSPICE verify the latchup immunity     

1.5 V high speed low power CMOS current sense amplifier

A 1.5 V high speed low power current sense amplifier for CMOS SRAMs is described. The design is based on the current mode approach and it can be fabricated using a standard CMOS process. The sensing speed is independent of the bit and data line capacitances and no equalisation is needed during the read access. HSPICE simulations have shown that the proposed circuit outperforms the recently reported circuits in terms of speed and average power dissipation     

Low-voltage, low-power BiCMOS digital circuits

A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages     

BiCMOS logic circuit for single-battery operation

A novel BiCMOS logic circuit is described that provides highspeed rail-to-rail operation with only one battery cell (1-1.5 V). The proposed circuit utilises a novel pull-down scheme that involves bootstrapping the base of the pull-down p-n-p bipolar junction transistor to a negative potential during the pull-down transient period. Circuit simulations have shown that the proposed circuit outperforms the transient-saturation full-swing BiCMOS and the bootstrapped bipolar circuits in terms of delay, power and cross-over capacitance for all simulated supply voltages