Linear viscoelastic properties of mixtures of 3- and 4-arm polybutadiene stars

The viscoelastic properties of a three-arm and a four-arm star polybutadiene with the same arm molecular weight (M_a) were studied. The zero-shear recoverable compliance (J⁰_e) and plateau modulus (G⁰_N) for these stars are the same. The zero-shear viscosity (η₀) of the three-arm star is 20% lower than that of the four-arm star. Mixtures of the stars had J⁰_e and G⁰_N unchanged. A $\text{50}\text{50}$ mixture of the three- and four-arm star was diluted with a low molecular weight linear polybutadiene. G⁰_N∝ø²; J⁰_e∝ø^?1 and M_e∝ø^?1, as expected for dilution with a θ-solvent.     

A continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to interferers

Receivers are being digitized in a quest for flexibility. Analog filters and programmable gain stages are being exchanged for digital processing at the price of a very challenging ADC. This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a /spl Sigma//spl Delta/ ADC. The novel filtering ADC is realized by adding a high-pass feedback path to a conventional /spl Sigma//spl Delta/ ADC while a compensating low-pass filter in the forward path maintains stability. As such, the ADC becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel. As a consequence, the ADC input range can be programmed dynamically to the level of the wanted signal only. This results in an input-referred dynamic range of 89 dB in 1-MHz bandwidth and an intentionally moderate output signal-to-noise-and-distortion ratio of 46-59 dB (depending on the programmed gain). The merged functionality enables a better overall power/performance balance for the receiver baseband. The design consumes less than 2 mW and active area is 0.14 mm/sup 2/ in a 0.18-/spl mu/m digital CMOS technology.     

A 12-b, 60-MSample/s cascaded folding and interpolating ADC

This paper describes the analysis, design, and experimental results of a 12-b, 60-MSample/s analog-to-digital converter (ADC). This ADC is based on a cascaded folding and interpolating architecture. The ADC is optimized for digital telecommunication applications. The cascaded folding and interpolating ADC architecture is introduced, optimizing the overall performance of this converter. The integrated track and hold amplifier enables an SNR>66 dB and a THD<72 dB, measured over an analog input signal bandwidth of 70 MHz. The ADC is realized in a 13-GHz, 1-μm BiCMOS process and measures 7 mm² , while dissipating 300 mW from a single 5.0 V supply