The effects of impact ionization on the operation of neighboringdevices and circuits

This paper examines the detrimental effects of excess majority carriers and photons induced by impact ionization on the operation of neighboring pn junctions, bipolar transistors, MOS transistors, and circuits. The experimental results show that in addition to an increase in the substrate surface potential due to the excess majority carriers, photons can lower the barrier of a pn junction and, as a consequence, shift the Gummel plot of an npn bipolar transistor. As for the neighboring circuits, an example in which the speed of an NMOS ring oscillator is retarded by impact ionization in a neighboring NMOS transistor is presented     

A negative Vth cell architecture for highly scalable,excellently noise-immune, and highly reliable NAND flash memories

A new, negative V_th cell architecture is proposed where both the erased and the programmed state have negative V_th. This architecture realizes highly scalable, excellently noise-immune, and highly reliable NAND flash memories. The program disturbance that limits the scaling of a local oxidation of silicon (LOCOS) width in a conventional NAND-type cell is drastically reduced. As a result, the scaling limit of the LOCOS width decreases from 0.56 to 0.45 μm, which leads to 20% isolation width reduction. The proposed cell is essential for the future scaled shallow trench isolated cells because improved program disturb characteristics can be obtained irrespective of the process technology or feature size. New circuit techniques, such as a PMOS drive column latch and a V_cc-bit-line shield sensing method are also utilized to realize the proposed cell operation. By using these novel circuit technologies, array noise, such as a source-line noise and an inter bit line capacitive coupling noise, are eliminated. Consequently, the V_th fluctuation due to array noise is reduced from 0.7 to 0.1 V, and the V_th distribution width decreases from 1.2 to 0.6 V. In addition to the smaller cell size and the high noise immunity, the proposed cell improves device reliability. The read disturb time increases by more than three orders of magnitude, and a highly reliable operation can be realized     

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byteeffective program speed

Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm² and an effective cell size of 1.1 μm²     

Harmonic analysis of a single-phase rectifier with a DC filter capacitor

A single-phase diode bridge rectifier with a filter capacitor on the dc side is often employed to convert ac input into a dc voltage. The input current of the rectifier contains harmonic currents which cause undesirable power line effects. Recently, a method using the time domain analysis has been proposed to calculate the harmonic currents of rectifier considering noninfinite capacitance, i.e., non-zero dc side impedance. This method is very accurate, but it requires a long computing time and a complicated algorithm. This paper proposes a new method that makes it possible to easily calculate the harmonic currents taking into account the effects of the ac and dc side impedances of rectifier. The proposed method, which is based on the frequency domain method, can be executed only with the algebraic computation, and its accuracy is quite high. The validity of the proposed method is also demonstrated by comparison with the results of time simulation.     

Restraint Method for Overcoming Heating Irregularity and Improving Heating Equipment Efficiency for Beverage Cans Using High‐Frequency Induction Heating

We were able to reduce heating irregularities in equipment for heating beverage cans by using the high‐frequency induction heating method and determining the resulting improvement in the heating efficiency. The heating irregularity between the top and bottom of the can was reduced to less than 3°C by improving the arrangement of the heating coils for the beverage can by thinning the winding and changing the circuit configuration. The efficiency of power conversion was improved from 93.0% to 97.4%. In this paper, the configuration of the equipment and the experimental results are reported.     

Design methodology of a robust ESD protection circuit for STIprocess 256 Mb NAND flash memory

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n^- junction with n⁺ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness     

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

A new configuration of single-phase symmetrical PWM AC choppervoltage controller

With the increased availability of power MOSFETs and insulated gate bipolar transistors, a new generation of simple choppers for AC inductive loads is foreseen. These new power semiconductors ease the use of forced commutations of thyristor switches to improve the supply power factor, even with highly inductive loads. The AC controllers with thyristor technology can be replaced by pulsewidth modulation (PWM) AC chopper controllers which have important advantages. In this paper, a symmetrical PWM AC chopper designed to operate with single-phase inductive loads with a reduced number of controlled switches is described. The operation as a variable voltage source of this converter is evaluated. This includes the conversion characteristics, harmonic generation, harmonic distortion factor, and input power factor. By digital simulation, these characteristics are investigated theoretically, and to correlate the measurements with theory, an experimental setup is presented to confirm the analytical analysis