A single-chip 12.7 Mchips/s digital IF BPSK direct sequencespread-spectrum transceiver in 1.2 μm CMOS

This paper describes a fully integrated digital-spread spectrum transceiver chip fabricated through MOSIS in 1.2 μm CMOS. It includes a baseband spread spectrum transmitter and a coherent intermediate frequency (IF) receiver consisting of a Costas loop, an acquisition loop for the pseudo-noise (PN) sequence, and a clock recovery loop with a 406.4 MHz onchip numerically controlled oscillator (NCO). The transceiver is capable of operating at a maximum IF sampling rate of 50.8 MS/s and a maximum chip rate of 12.7 R Mchips/s (Mcps) with selectable data rates of 100, 200, 400, and 800 kbps. At the maximum operating speed of 50.8 R MS/s, it dissipates 1.1 W. In an additive white Gaussian noise channel the IF receiver achieves a receiver output SNR within 1 dB of theory and can acquire code with a wide range of input SNR from -17 dB to over 30 dB. The transceiver chip has been interfaced to an RF up/down converter to demonstrate a wireless voice/data/video link operating in the 902-928 MHz band     

A low-power baseband receiver IC for frequency-hopped spreadspectrum communications

A baseband receiver IC which will be incorporated into a low-power frequency-hopped spread spectrum (FH/SS) transceiver for 902-928 MHz ISM band applications is presented. The chip performs noncoherent binary/quaternary frequency shift keying (FSK) demodulation, equal-gain diversity combining of dual antenna branches, and symbol and frequency synchronization. The chip also accommodates variable data rates from 2 to 160 kb/s, programmable hop rates, and tunable bandwidth Loop filters. The core area of the 1-μm CMOS chip is 3.9 mm×3.9 mm with a power consumption of 4.5 mW at 10 MHz from a 3-V supply. A baseband transceiver system utilizing this receiver chip for the prototype handset to demonstrate a point-to-point communication link is also described. Two XILINX FPGA chips were used to implement the remainder of the baseband transceiver functions, including frequency control logic for FSK modulation, acquisition control, data framing, symbol interleaving and deinterleaving, and interface control for data and voice     

DDFSGEN

This paper presents a functional compiler for the automatic design of Direct Digital Frequency Synthesizer (DDFS) integrated circuits (ICs) using a ROM based table look-up architecture. The compiler allows the user to specify high-level specifications such as the acceptable spurious response and it generates the IC architecture, floorplan, and layout. To construct the layout for different specifications, a library of parameterized macrocells has been developed in 1.2 m CMOS technology.A test chip with a quadrature DDFS module has been generated, using the compiler, and fabricated. The chip has two input signals: one is for frequency control while the other is for phase initialization. Input and output word lengths are 16 bits and 6 bits respectively. The chip complexity is approximately 12,000 transistors (DDFS core) and the die size is 4.8×2.9mm ². A maximum sample rate of 80 MHz has been attained implying a maximum sine (cosine) output frequency of 40 MHz and a frequency resolution of 1.22 kHz. The maximum spurious level measured is –46 dB.     

A 700-MHz 24-b pipelined accumulator in 1.2-μm CMOS forapplication as a numerically controlled oscillator

To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-μm CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from DC up to 350 MHz with a 41.7-Hz tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7-mm×1.7-mm IC dissipates 850 mW with a single 5-V supply, which is substantially lower than similar ECL and GaAs devices     

A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 μm triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6×6.1 mm². Power dissipation is 2 W at 200 MHz and 5 V     

A frequency-agile single-chip QAM modulator with beamformingdiversity

Architecture and circuit design techniques for VLSI implementation of a single-chip quadrature amplitude modulation (QAM) modulator with frequency agility and antenna beamforming characteristics are presented. In order to achieve reliable wireless communication modem function, the single chip all-digital QAM modulator implements various features, including high data rates with bandwidth efficiency, flexibility, meeting a wide variety of user throughput requirements with variable and width and data rates in a multi-user system, and robustness, incorporating diversity and redundancy techniques to guarantee robust communication for various operating environments. The modulator components consist of several digital processing building blocks, including various finite-impulse-response (FIR) filters, an innovative variable interpolation filter, a four-channel frequency translator with quadrature mixer for antenna beamforming diversity, a quadrature direct digital frequency synthesizer (QDDFS), a numerically controlled oscillator (NCO), a QAM formatter, a pseudorandom noise (PN) generator, an x/sinx filter, and a microcontroller interface. An optimized architecture and chip implementation for the variable modulator is derived and evaluated which will support symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally flexible IF frequencies up to 70 MHz with four-channel antenna beamforming function     

Analysis and design of a frequency-hopped spread-spectrumtransceiver for wireless personal communications

Personal communications services (PCS) require low-power radio technologies. One such transceiver architecture employing frequency-hopped spread-spectrum techniques is presented. System features such as antenna diversity with equal-gain combining and sequential hop combining are incorporated into the transceiver design to achieve robust wireless digital data transmission over fading channels. A direct-conversion architecture from radio frequency (RF) to baseband reduces the overall power consumption by eliminating intermediate frequency (IF) components. High-rate frequency hopping with frequency-shift keying (FSK) modulation is implemented using a direct digital frequency synthesis technique. A multiplierless correlation FSK detector, suitable for direct-conversion receivers, has been designed for quadrature noncoherent detection. Robust acquisition algorithms based on energy detection and pattern matching and tracking architectures using digital phase-locked loops are also described for system synchronization. The proposed transceiver is well-suited for low-power PCS applications and other portable wireless communications     

A 200 MHz CMOS pipelined multiplier-accumulator using aquasi-domino dynamic full-adder cell design

A bit-level pipelined 12 b×12 b two's complement multiplier with a 27 b accumulator has been designed and fabricated in 1.0 μm p-well CMOS technology. A new quasi N-P domino logic structure has been adopted to increase the throughput rate, and special pipeline structures were used in the accumulator to reduce the total latency. The chip complexity is approximately 10000 transistors and the die area is 2.5 mm×3.7 mm. The measured maximum clock rate is 200 MHz (i.e. 200 million multiply-accumulate operations per second), and the power-speed ratio is 6.5 mW/MHz. A unique output buffer design was also adopted to achieve 200 MHz off-chip communication while maintaining full CMOS logic levels     

Design techniques for silicon compiler implementations ofhigh-speed FIR digital filters

Architecture design techniques for implementing both single-rate and multirate high throughput finite impulse response (FIR) digital filters are explored, with an emphasis on those which are applicable to automated integrated circuit layout techniques. Various parallel architectures are examined based on the criteria of achievable throughput versus hardware complexity. Well-known techniques for reduced complexity and computation time are briefly summarized, followed by the introduction of several new techniques which offer further gains in both throughput and circuitry reduction. An architecture for mirror-symmetric polyphase filter banks is derived which exploits the coefficient symmetry between multiple filters to reduce hardware. Finally, the evolution of a silicon compiler which utilizes all of these techniques is presented, and results are given for compiled filters along with comparisons to other compiled and custom FIR filter chips     

Adaptive antenna arrays and equalization techniques for highbit-rate QAM receivers

Adaptive antenna arrays provide wireless communication systems with larger service capacity and higher link quality through frequency reuse and cochannel-interference rejection. In practice, the propagation environment is nonideal with shadowing, severe stationary, and fast multipath fading. In this paper, the combination of adaptive antenna arrays and equalization techniques is employed to achieve reliable high-bit-rate wireless communications in a multipath, multiinterferer environment. A low-complexity receiver structure is investigated for the feasibility of portable wireless communications applications. The performance of the proposed receiver is analyzed in both outdoor and indoor multipath conditions. The simulations show that, although the adaptive beamformer is capable of cancelling long-delayed multipath reflections in the outdoor environment within its degrees of freedom, the adaptive equalizer is mandatory to compensate for the residual of the outdoor environment or the short-delayed multipath reflections of the indoor environment to achieve a high-quality link and high data rate. The digital circuits of the proposed receiver are estimated to perform 50 billion operations per second (GOPS) of digital signal processing functions, and the gate count is estimated to be 100 000 for a custom integrated circuit implementation