Bias and temperature dependence of homogeneous hot-electroninjection from silicon into silicon dioxide at low voltages

In this paper, new homogeneous hot-electron injection data at 300 K and 77 K is provided covering applied voltages from well below to well above the Si-SiO₂ barrier height, and a wide range of oxide fields. We found that, in contrast to the MOSFET case, homogeneous injection shows two different regimes for accelerating voltages below and above the barrier height. A simple interpretation of the data is proposed, and supported by Monte Carlo (MC) simulations of the injection experiment. Essentially, the two regimes are the signature of a marked transition between an electron population mostly heated by the electric field, and a tail population created by additional but less efficient energy gain mechanisms, leading to a sharp transition in the carrier distribution function. The details of the bias and temperature dependence of injection are then interpreted as the combined effect of tunneling and carrier distribution. Furthermore, possible implications on MOSFET gate currents are briefly discussed     

Energy oscillations in electron transport across a triangularbarrier

Carrier transport across the semiconductor space-charge region of a silicon triangular barrier diode was investigated by a Monte Carlo simulation. Oscillations of the electron mean kinetic energy are observed as a function of position along the uphill slope of the barrier under bias. At a given point on the uphill slope, the energy distribution function shows an oscillatory behavior, with a periodicity corresponding to the optical phonon energy. These oscillations are shown to be due to the nonequilibrium dynamics of the electron interaction with optical phonons in the situation when other inelastic electron scattering processes are negligible. The energy oscillations are superimposed on a smooth cooling of the distribution in the transport toward the top of the barrier, as current flows through the system. A comparison with the thermionic theory quantifies the importance of nonequilibrium effects in short-range electronic transport     

Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs

State-of-the-art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the ultrathin silicon body (UTB) double-gate (DG) MOSFET and considering the main figures of merit (FOM) for the high-performance N-MOS transistor. The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short-channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field. As a consequence, the impact of surface roughness at the Si-oxide interface and the gate tunneling leakage current are substantially reduced compared to the case of highly doped bulk MOSFETs. According to our results, thanks to the suppression of gate leakage current, scaling of the UTB-DG MOSFET down to the 32 nm technology node appears possible adopting -based gate dielectrics. In spite of the improved mobility at given inversion charge density, the simulated on-currents are substantially lower than those required by the 2005 ITRS for the 45 and 32 nm nodes . Nonetheless, thanks to relaxed scaling of the oxide thickness, hence to reduced gate capacitance, the requirements in terms of intrinsic delay and power-delay product can be satisfied. The issue of variability is analyzed by evaluating the dependence of the key FOM on the variation of critical dimensions such as the thickness of the gate oxide and of the silicon layer.     

Influence of oxygen contamination on the surface tension of liquid tin

The surface tension of liquid tin has been measured by the sessile-drop technique as a function of temperature, in the range 232 T (°C) 800 and under different atmospheres. It is shown that oxygen strongly affects the surface tension values and that, under nominally very clean conditions, a considerable scatter of experimental results occurs. This scatter can be explained by taking into account kinetic factors, especially those related to the gaseous fluxes around the molten drop. By this procedure, a number of experimental results can be singled out, which corresponds to clean surface conditions. On the basis of these results, the following expression for surface tension politherm is proposed: (mN m^–1 = 581-0.13) (t-232).     

Simple and efficient modeling of EPROM writing

A simple and efficient model for first-order simulation of the writing of n-channel erasable programmable ROM (EPROM) cells is presented. It allows the current injected into the gate insulator of the cell transistor to be calculated, accounting (at first order) both for the nonMaxwellian form of the electron energy distribution and for the nonlocal nature of carrier heating. The model is implemented as a postprocessor of a two-dimensional device simulator, and it is validated by means of a comparison with experimental data obtained with devices with effective channel lengths ranging from 1.4 to 0.5 μm     

Comparison of Modeling Approaches for the Capacitance–Voltage and Current–Voltage Characteristics of Advanced Gate Stacks

In this paper, we compare the capacitance-voltage and current-voltage characteristics of gate stacks calculated with different simulation models developed by seven different research groups, including open and closed boundaries approaches to solve the Schroumldinger equation inside the stack. The comparison has been carried out on template device structures, including pure SiO₂ dielectrics and high-kappa stacks, forcing the use of the same physical parameters in all models. Although the models are based on different modeling assumptions, the discrepancies among results in terms of capacitance and leakage current are small. These discrepancies have been carefully investigated by analyzing the individual modeling parameters and the internal quantities (e.g., tunneling probabilities and subband energies) contributing to current and capacitance     

Injection efficiency of CHISEL gate currents in short MOS devices:physical mechanisms, device implications, and sensitivity totechnological parameters

This paper analyzes MOSFET gate currents in the so-called channel initiated secondary electron injection regime (CHISEL). A Monte Carlo model of the phenomenon is validated and then extensively used to explore CHISEL scaling laws. Results indicate that, compared to conventional channel hot electron injection (CHE), CHISEL exhibits a weaker dependence on channel length and a larger sensitivity to short channel effects. These results are confirmed experimentally and exhaustively explained with the help of simulations; furthermore, some of their possible detrimental consequences on the programming efficiency of CHISEL based flash cells are analyzed. Finally, the impact of channel doping, oxide thickness, and junction depth on CHISEL efficiency has been explored, and guidelines to maintain high injection efficiency in short devices are derived     

Non-local effects in p-MOSFET substrate hot-hole injectionexperiments

Extensive measurements of hot-hole injection probability from silicon into silicon dioxide covering a wide range of oxide fields and substrate biases are presented and compared with results previously published in the literature. It is found that, in the highly inhomogeneous electric fields typically needed to induce substrate hole injection, nonlocal effects take place that limit the possibility to accurately describe injection probability data by means of a unique set of lucky carrier model parameters     

Verification of electron distributions in silicon by means of hotcarrier luminescence measurements

This paper investigates the use of hot carrier luminescence (HCL) measurements as a mean for the verification of carrier energy distribution functions in submicron silicon devices subject to high electric fields. To this purpose, physically-based two-dimensional (2-D) simulations of the spectral distribution of HCL are compared with extensive experimental data on special purpose n⁺/n/n⁺ test structures that demonstrate lateral field profiles similar to real MOSFETs without the obscuring effects of a gate electrode. Good agreement between measured and simulated data is observed over wide channel length, bias, and temperature ranges, thus providing for the first time a direct verification of simulated electron energy distributions in a MOSFET-like environment