Low-voltage, low-power, low switching error, class-AB switched current memory cell

A class-AB switched current memory cell is proposed. The circuit decomposes the input signal into two components by a low-voltage class-AB current splitter and subsequently processes the individual signals by two low switching error class-A memory cells. As a consequence, the output current obtained by recombination of the separated signals can be higher than the bias current and features low error. Simulation results confirm that, for a 0.75 V supply, a 5 MS/s sampling frequency, and a 500 kHz sinusoidal input current having 400% modulation index, the proposed memory provides less than -45 dB THD output current with very low switching error.     

Compact low-voltage CMOS four-quadrant analogue multiplier

A compact architecture for a four-quadrant analogue multiplier circuit is presented. The circuit is formed by connecting common source amplifiers with a pair of differential flipped voltage followers. This results in a novel cancellation of the nonlinear terms in the sub-currents, leading to the desired four-quadrant analogue multiplier. The circuit combines low complexity with low-voltage operation and low static power consumption. Simulated results using a 0.35 mum CMOS process are provided     

0.75 V micro-power SI memory cell with feedthrough error reduction

A simple technique to realise a switched current memory cell operating from low supply voltage (0.75 V) with clock-feedthough (CFT) error reduction is presented. Unlike previous techniques that try to minimise current error by compensation at the output, this technique prevents the occurrence of current error by removing the feedthrough voltage from the input port of the memory transistor directly. As a result, the CFT error current at the output is almost completely eliminated employing a simple and compact circuit structure. Simulation results are given, showing good agreement to the theory.     

A 0.5-V, 2-nW, 55-dB DR,fourth-order bandpass filter using single branch biquads: An efficient design for FoM enhancement

A compact nano-power fourth-order bandpass filter operating from a 0.5 V supply, with an adjustable center frequency ranging from 125 Hz to 16 kHz, is presented. The filter is constituted from cascadable second-order circuit cells that are realized by a network of three transistors and two capacitors comprising only one branch of bias current. The measurement results of the filter fabricated in a 0.18-μm CMOS IC process indicate that, for a 1 kHz center frequency, a dynamic range of 55 dB is obtained from 2 nW power consumption. These results lead to best figure of merit achieved when compared to other existing designs to date.