Metalorganic chemical vapor deposition of silver thin films for future interconnects by direct liquid injection system

Deposition of Ag films by direct liquid injection-metal organic chemical vapor deposition (DLI-MOCVD) was chosen because this preparation method allows precise control of precursor flow and prevents early decomposition of the precursor as compared to the bubbler-delivery. Silver(I)-2,2-dimethyl-6,6,7,7,8,8,8-heptafluoro-3,5-octanedionato-triethylphosphine [Ag(fod)(PEt₃)] as the precursor for Ag CVD was studied, which is liquid at 30 °C. Ag films were grown on different substrates of SiO₂/Si and TiN/Si. Argon and nitrogen/hydrogen carrier gas was used in a cold wall reactor at a pressure of 50–500 Pa with deposition temperature ranging between 220 °C and 350 °C. Ag films deposited on a TiN/Si diffusion barrier layer have favorable properties over films deposited on SiO₂/Si substrate. At lower temperature (220 °C), film growth is essentially reaction-limited on SiO₂ substrate. Significant dependence of the surface morphology on the deposition conditions exists in our experiments. According to XPS analysis pure Ag films are deposited by DLI-MOCVD at 250 °C by using argon as carrier gas.     

Evaluation of electron beam welding technique for the integration of robust sensor elements into high-pressure automotive systems

For “on board” diagnosis purposes of the injected fuel quantity flow sensitive elements based on the thermo-resistive measurement principle were integrated into finished Common Rail injection nozzles of valve-covered orifice (VCO) or mini-sac hole (MSH) class. Electron-discharge machining as well as electron beam welding technique are key technologies for a reliable integration procedure. To demonstrate negligible influence on the hydraulic performance of the nozzle after modification an optical measurement set-up is used to record temporally resolved the propagation of the spray patterns ejected from the six injection holes simultaneously. From these investigations the impact on the structural distortion of the valve caused by the welding seam is proved as its position can be directly linked to any chances in spray performance of each individual injection hole. Reducing the energy input during the electron beam welding lowers substantially the asymmetry in spray patterns from hole to hole as the needle uncovers the six injection holes more symmetrically. Besides this important finding, the numerical calculations indicate that the implementation of the sensor chip slightly amplifies the asymmetry induced by the welding process due to an additional weakening of the nozzle body which is confirmed experimentally. Despite these challenges, however, it is demonstrated that appropriate parameters for the integration procedure can be found affecting the hydraulic performance negligible compared to the original state.     

Design based failure analysis and yield improvement in CMOS-circuits

In this paper we show that defect simulation is a basis for yield enhancement strategies. These strategies involve identification of the yield detractors (i.e. identification of spot defect characteristics) and yield oriented layout design, which uses information about defects. Information about key yield detractors can be obtained in a time and cost efficient manner using defect simulation. By comparison of process variants and of SRAMs with different layouts, the sensitivity of the method for process changes as well as for design differences is illustrated. This leads to the conclusion that the defect and yield simulation tools can be used for yield oriented design. The enormous cost and time savings demonstrated in this work give a signal to enforce the introduction of design based failure simulation methods into the yield learning process.     

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions

To meet the widely varying speed and power requirements of multifunctional mobile devices, an appropriate combination of technology features, circuit-level low-power techniques, and system architecture is implemented in a GSM/Edge baseband processor with multimedia and mixed-signal extensions. Power reduction techniques and performance requirements are derived from an analysis of relevant use cases and applications. The 44 mm² baseband processor is fabricated in a 90-nm low-power CMOS technology with triple-well option and dual-gate oxide core devices. The ARM926 core achieves a maximum clock frequency of 380 MHz at 1.4-V supply due to the usage of thin oxide (1.6 nm) devices. Power dissipation can be adapted to the performance requirements by means of combined voltage and frequency scaling to reduce active power consumption in medium-performance mode by 68%. To reduce leakage currents during standby mode, large SRAM blocks, nFET sleep transistors, and circuit components with relaxed performance requirements are implemented using devices with 2.2-nm gate oxide thickness     

Field-coupled computing in magnetic multilayers

This paper presents a computational study of ion-beam patterned cobalt-platinum multilayers, which could be used for field-coupled computing. We use micromagnetic simulations to reproduce measured hysteresis curves. This parameterized micromagnetic simulator then will be used for simulating interacting magnetic dots. We demonstrate how logic gates can be built from such coupled dots. We also show how electrical wires—placed beneath or above the magnetic dots—can provide a magnetic field, which propagates the magnetic signals.     

Influence of MOSFET I-V characteristics onswitching delay time of CMOS inverters after hot-carriers stress

The relationship between hot-carrier degradation in MOSFETs and CMOS inverters is studied. It is found that the device degradation characterized as the widely used bias points correlates poorly with the inverter degradation. The use of new bias points that are more meaningful for circuit performance is proposed. A simple equation for calculating the degradation of the propagation delay is developed     

Fast power-efficient circuit-block switch-off scheme

A methodology is proposed for glitch-free power switching of unused circuit blocks in leakage dominated deep-submicrometre technologies. With respect to conventional non-glitch-free approaches, significantly faster settling time and lower power consumption during the activation of the block are obtained.     

A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs

We present a novel principle for 1/f noise reduction in linear analog CMOS ICs. The principle is experimentally demonstrated for a two-stage CMOS Miller operational amplifier in a standard 0.12-mum, 1.5-V digital CMOS technology. A threefold 1/f noise reduction (5 dB) is achieved at 10 Hz compared with a reference circuit. The impact of the principle on the circuit performance is investigated