The method of lines for the analysis of planar waveguides withfinite metallization thickness

The method of lines is extended to calculate waveguide structures with finite metallization thickness. The normally used range of metallization thickness is not a limit for the method. Particularly when calculating small or moderate thicknesses, it is possible to derive the dispersion constant with only one computed result. When using the optimal edge parameter, P_opt, for that computation, the deviation from the exact dispersion constant is less than 0.5%. The advantage of the method of lines is that only small line numbers are necessary. Hence, the computing time is very small     

The method of lines for the analysis of lossy planar waveguides

The method of lines is extended to calculate the losses of waveguide structures. Ohmic losses in metallizations (with frequency-dependent, extremely high dielectric constants) and dielectric losses are simultaneously considered. Despite the high ratios of the dielectric constants of the metallizations and the dielectrics, the analysis and numerical treatment are carried out accurately. Using nonequidistant discretizations the results are computed efficiently, and an approximate value of the propagation constant close to the exact value is found by extrapolation. The phase constant deviates less than 0.5%. The attenuation may deviate up to 2%. The advantages of the method of lines are a small computation time and, due to the analytical solutions of the fields in one direction, a very good approach to the fields inside the strip as well as to the strong fields directly adjacent at the edges. The results for a single microstrip line are shown and compared with those of other authors     

Fabrication of Application Specific Integrated Passive Devices Using Wafer Level Packaging Technologies

Integrated passives have become increasingly popular in recent years. Especially wafer level packaging technologies offer an interesting variety of different possibilities for the implementation of integrated passive components. In this context, particularly the fabrication of integrated passive devices (IPDs) represents a promising solution regarding the reduction of size and assembly costs of electronic systems in package (SiP). IPDs combine different passive components (R,L ,C ) in one subcomponent to be assembled in one step by standard technologies like surface mount device (SMD) or flip chip. In this paper, the wafer level thin film fabrication of integrated passive devices (WL-IPDs) will be discussed. After a brief overview of the different possibilities for the realization of IPDs using wafer level packaging technologies two fabricated WL-IPDs will be presented. Design, technological realization, as well as results from the electrical characterization will be discussed.