ZF从设计概念到系列产品的系统供应者

ZF集团在传动系统、转向器和底盘技术方面处于独特的地位,根据这方面特点,我们把各个子公司,组成一个完整的系统,本文将介绍ZF帕骚（Passau）在非公路传动系统和轴系方面处于领先地位的情况。     

Architecture and circuit design of a 6-GOPS signal processor forQAM demodulator applications

A QAM processor for applications in QAM demodulators with baud rates of up to 60 Mbaud and modulation schemes of up to 1024 QAM has been implemented on a single chip. The chip performs 11-tap complex-valued adaptive time-domain equalization and the complete digital base-band signal processing of high-capacity QAM demodulators. This includes frequency-domain slope equalization and the digital parts of the timing and carrier recovery as well as the gain and offset control for the A-to-D converters. The equalizer can be operated in baud spaced and half-baud spaced mode and can also be applied for cross-polarization interference cancellation. The computational power of the QAM processor exceeds 6 giga-multiply-accumulate operations per second. Fabricated in an 1.0-μm CMOS technology on a silicon area of 185 mm² this 800 K-transistor chip demonstrates the potential of such low-cost technologies. The maximum clock frequency under worst-case conditions is 60 MHz. The corresponding power dissipation is 4.2 W     

A single-chip adaptive DPCM video codec

A differential pulse-code modulation (DPCM) video codec with two-dimensional intrafield prediction and adaptive quantizer is presented. An approach for the arithmetic implementation of the DPCM structure and the design of a test chip, fabricated in a 1.5 μm CMOS technology, is described. This is the first VLSI realization of a DPCM codec with adaptive quantizer. For the test chip transmitter or receiver mode, application as part of a three-dimensional interframe codec and processing of luminance or chrominance signals are optional. A line buffer and ten different quantizer characteristics are realized on-chip. Correct operation has been verified up to 26 MHz