Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits

The placement of substrate contacts in epi and non-epi technologies is analyzed in order to control and reduce the substrate noise amplitude and spreading. The choice of small or large substrate contacts or rings for each of the two major technologies is highlighted. Design guidelines for placing substrate contacts so as to improve the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.     

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.     

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.     

Applying Analog Techniques in Digital CMOS Buffers to Improve Speed and Noise Immunity

A digital CMOS buffer circuit with avoltage transfer characteristic (VTC) with lowthreshold voltage detection, hysteresis, andhigh noise immunity is presented. The circuitis capable of restoring slow transition timesand distorted input signals with a minimumdelay penalty, offering at the same time highnoise immunity to glitches induced eitherthrough capacitive coupling or from the powersupply lines. The high noise immunity of theproposed buffer circuit is achieved usingdifferential mode rejection and a differentialredundant circuit architecture.     

Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling

A simple, yet physically intuitive macrolevel model is presented to identify the dominant substrate coupling mechanism at the early stages of the design process, while simultaneously considering multiple parameters. Furthermore, the sensitivity of substrate noise to these parameters is evaluated, demonstrating the nonmonotonic dependence of noise on rise time. The design implications of the proposed analysis are discussed, identifying the preferred noise reduction technique for a specific set of operating points.