Full CMOS continuous time filters for GSM applications

This paper describes full cmoscontinuous time filter design techniques which can meet the specifications commonly set for gsmapplications. First several cmosfilter design techniques are overviewed. The ota-ctechnique is discussed to some more detail. To overcome the main drawback of the lower total harmonic distortion in ota-ctechniques very linear operational transconductance amplifiers (ota)are required. Such an ota,together with the applied linearisation techniques is discussed. To fulfil high accuracy in cut- off frequencies of the filter an active tuning system is necessary. A new on- chip tuning system is presented. The paper concludes with a practical design example for the gsmsystem. Therein the different ota-ctechniques discussed are illustrated.     

A four-channel digital signal processor in 1.2-μm CMOS withon-chip D/A and A/D conversion serving four speech channels in anew-generation subscriber line circuit

The major component for a new-generation line circuit was designed and fabricated in a 1.2-μm CMOS technology. The circuit includes digital signal processing of receive (RX) and transmit (TX) signals as well as the analog front end of four subscriber lines to a PCM (pulse code modulation) digital exchange. The device operates on a single 5-V power supply. The four-channel digital signal-processor including the analog front ends is fabricated on a 40-mm² 1.2-μm CMOS die area. The DSP functions, the RX and TX filters, the decimator, the interpolator, and the A/μ-law transcoder are included as independent data paths, one for the TX and RX filters, one for the decimator, and another for the interpolator, the digital sigma-delta modulator, and the transcoder. The on-chip analog front end contains a notch filter to cancel the 12/16-kHz payphone signal, a switched-capacitor PDM A/D and D/A converter, and smoothing filters. On the first measured samples, the signal-to-distortion ratio is measured to be 33 dB at -45 dBmo for -7 dB gain setting     

A transistor-only switched current sigma-delta A/D converter for aCMOS speech CODEC

This paper describes the design and measurement results of a 1-b A/D converter based on a transistor-only switched current (SI) second-order sigma-delta modulator. The 1-b A/D converter was simulated and processed in ES2 1.5 μm CMOS technology. The second-order filter is based on class AB switched current-integrators. The analog current memory cells in the integrator are optimized for linear operation with a strong class AB overlap region to avoid class B operation and cross-over distortion. Measurement results on the first silicon performing 11-b resolution show that this circuit technique is promising for speech CODEC A/D conversion     

Wireless telecom silicon integration: analog design for radio,baseband and speech spectrum

The application today, pushing analog design for CMOS and RFbipolar into new frontiers is definitely the mobile radio telephony. New telecom systems like GSM, PCN, DECT, DCS, Wireless in the loop ... are all developing very rapidly and will enable us very soon to organise a complete telephone network with full coverage for your car, as well as in your kitchen and on your office desk. In Europe the major telecom companies have worked together to establish one common standard for cellular mobile radio communications at 900 MHz. Similar things are happening for other wireless personal communication systems. Basically the cellular radio telephone, the wireless PABX and the wireless SLIC are bringing the same challenges to analog circuit design: maximum integration of the basic radio functions into 1 or 2 silicon chips, CMOS, Bipolar or BiCMOS or GaAs. The analog circuit designer for radio telephone applications will need all the state of the art analog design knowhow available today, from RFmixers and GHz range low noise amplifiers and local oscillator synthesizers over base band 100 kHz CMOS analog to low frequency speech analog to digital conversion. And for all these circuits the message is: minimum power consumption for battery autonomy, minimum silicon area for maximum functional integration per die to obtain a small, low cost pocket size radio telephone.     

ECL-CMOS and CMOS-ECL interface in 1.2-μm CMOS for 150-MHzdigital ECL data transmission systems

The design of a full-CMOS circuit that converts voltage signals from those used for emitter-coupled logic (ECL) to CMOS and vice versa, for use in digital data transmissions with clock frequencies up to 150 MHz, is described. Extremely high performances are obtained due to a novel circuit principle, in both the ECL-to-CMOS convertor and the CMOS-to-ECL convertor. A wideband CMOS amplifier used in the ECL-to-CMOS convertor, incorporating a current injection technique to increase the bandwidth of the circuit, is also presented. A circuit principle is presented to realize an extremely fast CMOS-to-ECL conversion, based on a current switching technique and charge injection to compensate the large output capacitance. Both circuits make use of replica biasing to ensure maximum switching speed in the ECL-to-CMOS convertor and correct ECL output levels in the CMOS-to-ECL convertor. An ECL-CMOS-ECL repeater has been designed in a 1.2-μm double-metal CMOS process     

CMOS LED driver and PIN receiver for fiber optical communication at 150 mbit/sec

A test chip for an integrated full CMOS LED driver has been realized with a modulation current of 60 mA at a maximum bit rate of 155 Mb/s. A CMOS receiver is evaluated to amplify PIN diode photocurrents less than 10 µA at the same bit rate of 155 Mb/s. Both circuits are integrated on one chip. The circuit has been developed in a 0.8-µm digital CMOS process.     

A novel active feedback flyback with only 100-mV inductive overshoot for a standard low-voltage CMOS inductive load driver, in a single-chip controller for 73 relays in a POTS/ADSL splitter application

This paper presents an inductive load driver. The circuit is realized in a standard low-voltage CMOS process: as the coil freewheels when the driver is switched off, the circuit clamps the output voltage at 100 mV above the power supply. Hence, no high-voltage technology or high-voltage tolerant circuit is required. 73 drivers are integrated in an ASIC, controlling 73 relays for a test access function on a POTS/ADSL splitter filter board. The driver also performs output voltage slope control and has an elegant, effective short-circuit protection.     

Trends in silicon radio large scale integration: zero IF receiver!Zero I&Q transmitter! Zero discrete passives!

After 10 years of advances in silicon RF integration, what used to be an art is becoming a “normal practice”. Historically, RF design was the art of s-parameters, shielding, impedance matching, and standing wave ratios. Modern silicon RFICs are designed using the same SPICE-like tools as in low-frequency analog ICs with the addition of important software for system-level simulation and mixer circuit noise analysis. New RF design practices away from the 50 ohm culture, novel chip architectures, and powerful technological advances will drive radio integration toward the ultimate single-chip phone. The obstacles in this quest are high system requirements on noise figure, substrate crosstalk, and parasitic coupling, not the silicon IC technology     

CMOS LED-driver and PIN-receiver for fiber optical communication at 155 Mbit/s

A test chip for an integrated full cmos led driver has been realized with a modulation current of 60 mA at a maximum bit rate of 155 Mbit/s. A cmos receiver is evaluated to amplify pin diode photo currents less than 10 μA at the same bit rate of 155 Mbit/s. Both circuits are integrated on one chip. The circuit has been developed in a 0.8 μm digital cmos process.