A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously.     

Dietary Guar Gum Reduces Lymph Flow and Diminishes Lipid Transport in Thoracic Duct-Cannulated Rats

Guar gum has a well-recognized hypolipidemic effect. This effect is thought to be due to the physicochemical properties of guar gum, which may cause changes in adsorption of lipids or the viscosity of the intestinal contents. Guar gum is a non-specific absorption inhibitor of any type of lipid-soluble compound. Permanent lymph duct cannulation was performed on rats to investigate the effects of dietary guar gum on lymph flow and lipid transport. Rats fed a 5% guar gum diet were compared with those fed a 5% cellulose diet, and lymph was collected after feeding. The water-holding capacity (WHC), settling volume in water (SV), and viscosity of guar gum were compared with those of cellulose. Rats fed with the guar gum diet had significantly lower lymph flow and lymphatic lipid transport than did rats fed with the cellulose diet. The WHC, SV, and viscosity of guar gum were significantly higher than those of cellulose. We propose that dietary guar gum reduces lymph flow and thereby diminishes lipid transport by means of its physicochemical properties related to water behavior in the intestine.     

Rice α-globulin decreases serum cholesterol concentrations in rats fed a hypercholesterolemic diet and ameliorates atherosclerotic lesions in apolipoprotein E-deficient mice

The hypocholesterolemic and antiatherogenic effects of rice α-globulin remain unclear. We investigated the hypocholesterolemic effect of rice α-globulin in rats fed a hypercholesterolemic diet. The rats were divided into 4 groups and were orally administrated the following three proteins or a vehicle for 4 weeks: rice protein, rice α-globulin, or soy β-conglycinin at a dose of 100 mg/kg body weight or carboxymethylcellulose to the control rats. In the rice α-globulin group, serum cholesterol concentrations were 28% lower than the control group and fecal neutral steroid excretion was increased by 30%. The hypocholesterolemic effect of rice α-globulin was equal to soy β-conglycinin in SD rats fed the hypercholesterolemic diet. However, the serum cholesterol concentrations in the rice protein group did not change compared to the control group. To investigate the antiatherogenic effects of rice α-globulin, male apolipoprotein E-deficient mice were orally administered the same dose of rice α-globulin for 9 weeks. The en face lesion area in the aorta was 46% lower than in the control group. In conclusion, administration of rice α-globulin improves hypercholesterolemia in rats fed a hypercholesterolemic diet by increasing the fecal excretion of neutral sterols, and inhibits atherosclerosis development in apolipoprotein E-deficient mice. The anti-atherosclerotic effect exerts by mechanism(s) other than the regulation of serum MCP-1 and NO concentrations.     

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm² 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ?m². An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.     

A 32-Mb chain FeRAM with segment/stitch array architecture

This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-/spl mu/m three-metal CMOS technology. A small die size of 96 mm/sup 2/ and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using capacitor-on-plug technology but also by two key techniques that utilize the three-metal process: 1) a compact memory cell block structure that eliminates plateline area and reduces block selector area and 2) the segment/stitch array architecture which reduces the area of row decoders and plate drivers. As a result, the average cell size shrinks to 1.875 /spl mu/m/sup 2/, which is smaller than a 0.13-/spl mu/m SRAM cell, and the chip size is reduced to 70% of the chain FeRAM of conventional configuration with two-metal process. Moreover, a power-on/off sequence suitable to the chain FeRAM is introduced to protect the memory cell data from the startup noise. Compatibility with low-power SRAM is a key issue for mobile applications. The low-standby-current bias generator is introduced and the standby current of the chip is suppressed to 3 /spl mu/A. The modified address access mode is also adopted to eliminate the need of intentional address transition after the startup of the chip. The chip enable access time was 50 ns and cycle time was 75 ns at 3.0-V V/sub dd/.     

An experimental DRAM with a NAND-structured cell

An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 μm², using 0.4-μm CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm², which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved