Latched domino CMOS logic

A new gate configuration: the latched domino (Idomino) CMOS gate is described in the letter. It can be used to alleviate the inversion problem inherent in domino CMOS logic. It retains the speed advantages of domino logic while improving logic flexibility and reducing area. The gate is compatible with standard domino logic.     

Differential pass transistor logic in CMOS technology

Differential pass transistor logic is described in the letter. This configuration results in better silicon area efficiency and higher speed of operation than conventional CMOS pass transistor logic.     

A family of user-programmable peripherals with a functional unitarchitecture

A family of user-programmable peripherals, utilizing an integration strategy based on a programmable system device (PSD) concept, is described. Specifically, PSD is an efficient and highly configurable integration of high-density memory and LSI level logic blocks. The configurability is derived by providing programmable logic and programmable interconnect. PSDX is the first PSD family of programmable microcontroller peripherals; it integrates 256 kb to 1 Mb of EPROM, 16 kb of SRAM, a 28-input by 42-product term programmable logic device (PLD), and flexible I/O ports. This family is primarily targeted for embedded microcontroller applications. Using one PSD device it is possible to replace all the core peripherals in the system and, as a result, achieve a reduction in components, power dissipation, and overall system cost. The flexible architecture is achieved by providing 46 configuration options, which allows the PSD to interface with virtually any 8- or 16-b microcontroller. The integration is made possible by developing a special configurability and testability scheme. These parts are realized on a 1.2-μm CMOS EPROM process     

Testability enhancement of domino CMOS logic

A simple circuit technique to enhance the testability of domino CMOS circuits is presented. The fact that domino CMOS gates always have their outputs precharged low enables one to test for output stuck-at-one faults by a simple modification of the domino gate.     

A bipolar load CMOS SRAM cell for embedded applications

This paper presents a new SRAM cell concept which offers cell scaling without requiring complicated, specialized processing technology. The proposed cell utilizes a bipolar transistor in an open-base (base is floating) configuration as a simple means of realizing a high impedance load element. The Bipolar Transistor Load (BTL) is designed such that its open base current (the holding current) is always large enough to compensate for the NMOS pull-down transistor leakage current. The load holding current and the pull-down transistor leakage current are based on the same physical mechanism, namely thermal generation, as a result the load exhibits current tracking properties over varying process and temperature conditions. The cell size is 72 μm² with typical 0.8 μm design rules, which is about a 60% reduction as compared to a standard 6-T full CMOS cell. The operating properties of the BTL cell were studied analytically and characterized experimentally. The BTL SRAM module can be easily integrated as part of any CMOS process with minimal additional processing steps     

A 50-ns 256 K CMOS split-gate EPROM

A high-speed 32 K×8 CMOS EPROM has been designed and implemented in a polycide 1.2-μm n-well epi CMOS technology. A high-read-current split-gate EPROM cell combined with address transition detection-based SRAM-like precharge, equalization, and clocked differential sensing schemes has resulted in a typical address access time of less than 50 ns. The typical power dissipation at 18.2 MHz is 60 mW. Row redundancy is used to enhance the yield and the part has been designed to be compatible with plastic packaging