40 Gbit/s limiting output buffer in 80 nm CMOS

A 40 Gbit/s 1V limiting output buffer for an AC-coupled 50 /spl Omega/ load with a differential output swing of 660 mV and a gain of 18 dB is presented. A power consumption of only 24 mW and a simulated risetime of 11 ps are achieved by means of a systematic buffer optimisation.     

Comparison of simulation and measurement of dynamic fiber-coupling effects for high-speed multimode VCSELs

Static and dynamic measurements are performed with GaAs oxide-confined vertical-cavity surface-emitting lasers (VCSELs), using multimode fibers with a core diameter of 50 and 62.5 /spl mu/m and different numerical apertures (NAs). They show that a small NA can have a severe impact on the eye opening and thus also on the bit-error rate. The measurements are analyzed with a spatiotemporal two-dimensional (2-D) multimode VCSEL model. The required parameter extraction for the model is verified with small- and large-signal measurements. The analysis shows that the change of the eye opening can be explained by the interaction between the mode- and the current-injection profile, carrier diffusion, and intermodal gain compression (IGC). IGC increases differences in the modal power distribution caused by the interaction between the mode profiles and the current-injection profile. Carrier diffusion is able to compensate these increased differences of the modal power distribution. Its impact, however, on dynamic changes caused by IGC is moderate.     

30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS technology. All impedance matching, bias, and filter elements are implemented on the chip, which has a compact size of 0.5 mm/spl times/0.47 mm. The circuit covers a radio frequency range from 30 to 40 GHz. At a RF frequency of 35 GHz, an intermediate frequency of 2.5 GHz and a local-oscillator (LO) power of 7.5 dBm, a conversion loss of 4.6 dB, a single-sideband (SSB) noise figure (NF) of 7.9 dB, an 1-dB input compression point of -6 dBm, and a third-order intercept point at the input of 2 dBm were measured. At lower LO power of 0 dBm, a conversion loss of 6.3 dBm and an SSB NF of 9.7 dB were measured, making the mixer an excellent candidate for low power-consuming wireless local-area networks. All results include the pad parasitics. To the knowledge of the authors, this is the first CMOS mixer operating at millimeter-wave frequencies. The achieved conversion loss is even lower than for passive MMIC mixers using leading edge III/V technologies, showing the excellent suitability of digital CMOS technology for analog circuits at millimeter-wave frequencies.     

A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

The implemented static frequency divider provides quadrature (Q) clock outputs and divides frequencies up to 44GHz. The core divider circuit consists of two current-mode logic (CML) latches and consumes 3.2mW from a 1.1-V supply. The divided outputs result in a peak-to-peak and rms jitter of 6.3 and 0.8ps, respectively, and the maximum phase mismatch between the in-phase (I) and Q-outputs amounts to 1ps at an input frequency of 40GHz. The high division frequency is achieved by employing resistive loads, inductive peaking, and optimizing the circuit layout for reduced parasitic capacitances in the latches. The core divider consumes a chip area of 30/spl mu/m/spl times/40/spl mu/m only.     

Design of low-power fast VCSEL drivers for high-density links in 90-nm SOI CMOS

The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser drivers a challenging task. Hence, a detailed comparison of three basic driver architectures, namely, common source (CS), CS with source degeneration, and source follower (SF) is presented using transistor models including short channel effects. Based on this comparison, two power-optimized driver topologies are implemented in a 90-nm silicon-on-insulator CMOS technology. The SF driver features a bandwidth of 18 GHz on a 50-/spl Omega/ load. The required chip area is only 140 /spl mu/m/spl times/140 /spl mu/m, which is very beneficial for high-density short-distance optical interconnects. This allows a data rate of 12.5 Gb/s at a bit error ratio of less than 10/sup -12/ to be achieved even with a 10-Gb/s oxide confined vertical-cavity surface-emitting laser (VCSEL). The power consumption is 27 mW. The drivers were optimized for maximal eye opening by applying a fast and accurate VCSEL model.     

A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS

This paper describes the design of a transimpedance amplifier (TIA) for a low-power, short-distance, high-density fiber-optic interconnect communication system. The single-ended circuit has been designed in an 80-nm digital CMOS process and consumes only 2.2 mW from a 1-V supply. The measured results show a transimpedance gain of 52 dB/spl Omega/ and a large bandwidth of 20 GHz. This work presents the highest bandwidth at the lowest power consumption for CMOS transimpedance amplifiers reported to date.