Increasing the current-handling capability of TIL GTO thyristors up to its limits—I. Analysis and design

A rigorous analysis of the novel two-interdigitation levels gate turn-off thyristors (TIL GTOs) is performed with the aim of increasing their current-handling capability up to their limits. A closed form relationship correlating the maximum controllable anode current I_ATO with the peculiar geometry of the TIL pattern and the main technological parameters is obtained. Design rules with general validity are set out for the worst premises and correlated with the physics underlying the peculiar behaviour of TIL GTOs in various modes of operation. Based on the advanced three-transistor model of the TIL GTO structure, the basic theory underlying the device behaviour in the ‘on’ state is developed. The mechanisms of the current balancing between the two types of p-n-p-n sections (standard and quasi-non-regenerative) constituting the TIL GTO structure are disclosed. The broad implications of the current balancing on the current-handling capability of devices are presented in detail. The optimized design criteria were applied to 4 × 4 mm area, TO-220-packed TIL GTOs. The projected value of I_ATO in the worst case is 45 A, which would be the highest value of I_ATO ever reported in the literature for this class of GTOs (identical device area and case).     

The importance of the n-base in p-n-p-n-like structures subjectedto dV/dt ramps

A simple yet thorough analysis of physical effects induced in p-n-p-n-like silicon structures by the high rate of the OFF-state forward anode voltage rise (dV/dt) is discussed. The importance of n-base parameters in shaping the faulty triggering of thyristors subjected to dV/dt ramps is clearly demonstrated. The main implications of the findings for thyristor physics and design are also outlined     

Double-interdigitated (TIL) bipolar power transistors with lightlydoped collectors

The results of an investigation concerning the implementation of the two-interdigitation-level (TIL) concept in TO-3-packaged, triple-diffused bipolar power n-p-n transistors with lightly doped collector are discussed. It is demonstrated that the TIL concept, which offers a fair balance between manufacturability ease/cost effectiveness and overall electrical performances, allows for an increase of both the DC and small-signal current gains and the voltage ratings of bipolar transistors. The peculiarities of the ON-state current carrying mechanism in TIL-type transistors was investigated and its impact on device behavior was also assessed     

Increasing IATO in TIL GTO thyristors

The work reports the development of a 4×4 mm-area TIL GTO switch with a maximum controllable anode current IATO = 45 A, which exceeds by 80% the peak reported value in the literature for this class of GTOs. The maximum turn-off gain obtainable in the vicinity of IATO is Koff = 17. The mechanisms underlying this drastic boost of IATO and the broad implications of reported results are outlined in the letter.     

Monitoring the final on-zone dynamics in TIL GTO thyristors

An original method that spotlights the increase of the final on-zone of the squeezed plasma with the level of anode current is described and implemented in the gated turn-off experimental investigation of TO-220-packaged, high-voltage TIL GTO thyristors.     

Two-dimensional computer design of dual-ring thyristors

The main 2-dimensional equations are presented for the basic computer model of dual-ring amplifying gate thyristors (d.r.t.). These criteria ensure the maintenance of the very high di/dt capability of these devices in any possible triggering conditions.     

Computer-aided experimental investigation of the correct turn-on in thyristors with amplifying gate

A 2-dimensional computer model has been developed for the analysis of the amplifying gate thyristors correct turn-on at the auxiliary emitter prior to the main one. The results of investigation were used in the design of devices having essentially the same di/dt high capability in any possible turn-on conditions.     

A simple model for dry oxidation of silicon ion implanted with high doses of arsenic

Journal of Materials Science Letters -     

Simple method for increasing current gain and voltage ratings of power transistors

The letter presents a simple design/technological approach which increases both the (DC and small-signal) current gains and the voltage ratings (VCEO(SVS) and VCBO) of power bipolar transistors. The novel method offers a fair balance between cost-effectiveness and overall device performance, the electro-thermal reliability included.     

Increasing the current-handling capability of TIL GTO thyristors up to its limits—II. Experimental

The theoretical analysis and the developed design criteria for TIL GTO thyristors presented in the first part of this study (Paper I) are validated experimentally. The TO-220-packaged, high-voltage (V_DRM = V_RRM = 1000–1500 V) test TIL GTOs had a total cathode area of 8 mm², of which the area of deep-diffused cathode zones amounted to 3.5 mm². The implementation of optimized technological/geometrical ratios for TIL gate-cathode configuration yielded TIL GTO thyristors with a maximum controllable anode current of 55 A, which is the highest value of I_ATO reported thus far in the open literature for this class of GTOs (identical device area and case). All technological factors and physical effects underlying this achievement are analyzed in detail in this work. The current balancing between the two types of elementary p-n-p-n sections (standard and quasi-nonregenerative) constituting the vertical structure of the novel device is checked experimentally and the impact of this peculiar effect on current-handling capability of TIL GTOs is assessed both qualitatively and quantitatively. The boost of I_ATO up to its limits, ultimately dictated by the thermal impedance junction-to-case Z_thj?c TO-220-packages, was accompanied by a significant increase of the peak turn-off gain (10–20) of these devices at higher levels of anode current and by failure-safe operation of TIL GTOs at high commutation frequencies (up to hundreds of kHz) under heavy load conditions. The developed devices possess an excellent turn-on sensitivity and a high immunity to noise (high dV/dt capability). All the results of this work show clearly that sought-for benefits could be obtained by using the optimized double-interdigitated (TIL) gate-cathode pattern in GTO thyristors. The notation used is the same as in Paper I.