A large-signal very low-distortion transconductor forhigh-frequency continuous-time filters

A high-frequency large-signal very low-distortion voltage-to-current transducer is presented. The total harmonic distortion (THD), for supply voltages of only ±2.5 V, is smaller than 0.1% for fully differential input signals up to 2.4 V peak to peak (V_pp). The dynamic range is on the order of 89 dB with the transconductor noise integrated over a bandwidth of 1 MHz. Moreover, this structure presents low sensitivity to transistor mismatches. An operational transconductance amplifier (OTA), based on this transconductor, has been used in an adjustable quality factor 1.8-MHz biquadratic continuous-time filter. The quality factor Q is controlled, from 2 to 50, with a novel current-source configuration. Both the OTA and the filter have been fabricated in a CMOS 3-μm n-well process     

Frequency planning and synthesizer architectures for multiband OFDM UWB radios

This work presents an analysis on frequency planning and synthesis for multiband (MB) orthogonal frequency-division multiplexing (OFDM) ultra-wideband (UWB) radios operating in the range of 3.1-10.6 GHz. The most important specifications for the frequency synthesizer in an MB-OFDM UWB transceiver are provided. A synthesizer architecture for an existing frequency plan is introduced along with a discussion on its performance and implementation. An alternative frequency plan and its corresponding synthesizer architecture are also proposed. It is shown how this modified frequency plan leads to a significant simplification in the synthesizer realization. The feasible performance of both synthesizer architectures is evaluated through macromodel simulations using realistic models for the building blocks. Finally, system-level simulation results showing the impact of synthesizer spurs on the bit error rate performance of an MB-OFDM UWB receiver in the presence of interferers are provided. The presented results and discussion provide valuable insight for the implementation of a 3.1-10.6-GHz UWB synthesizer.     

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-/spl mu/m CMOS process; filter's area is 0.84 mm/sup 2/.     

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chipautomatic tuning

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V_p-p). The complete system operates with supply voltages of ±2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5-μm n-well CMOS process     

A CMOS transconductance amplifier architecture with wide tuningrange for very low frequency applications

A pseudodifferential CMOS operational transconductance amplifier (OTA) with wide tuning range and large input voltage swing has been designed for very small G_M's (of the order of a few nanoamperes per volt). The OTA is based on a modified four-quadrant multiplier architecture with current division. A common-mode feedback circuit structure has been proposed and designed using floating-gate transistors to handle large differential signals. Large on-chip capacitors are emulated through impedance scaling circuits. The circuits, fabricated in a 1.2-μm CMOS process, have been used to design a fourth-order bandpass filter and a relaxation oscillator. Experimental results are in good agreement with the theoretical results     

Algorithmic ADC operating with a single reference voltage for PLL-based chemical sensing applications

This paper deals with the design of an algorithmic switched-capacitor analog-to-digital converter (ADC), operating with a single reference voltage, a single-ended amplifier, a single-ended comparator, and presenting a small input capacitance. The ADC requires two clock phases per conversion bit and N clock cycles to resolve the N-bits. The ADC achieves a measured peak signal-to-noise-ratio (SNR) of 49.9 dB and a peak signal-to-noise-and-distortion-ratio (SNDR) of 46.7 dB at P_in = ?6dBFS with a sampling rate of 0.25 MS/s. The measured differential-non-linearity and integral-non-linearity are within +0.6/?0.5 and +0.2/?0.5 LSB, respectively. The ADC power consumption is 300 μW and it is implemented in 90 nm CMOS technology with a single power supply of 1.2 V. The ADC saves power at system-level by requiring only a single reference voltage. At system level, this solution is therefore not only robust but competitive as well.     

An On-Chip Spectrum Analyzer for Analog Built-In Testing

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 m technology are presented to demonstrate the feasibility of the proposed BIT technique.Marcia G. Mendez-Rivera was born in Irapuato, Mexico in 1972. She received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico. in 1996, the M.Sc. degree from the Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico in 1998 and the M.Sc. from Texas A&M University, College Station in 2002. Her research interest is in the design and fabrication of analog and mixed-signal circuits.Alberto Valdes-Garcia born in 1978, grew up in San Mateo Atenco, Mexico. He received the B.S. in Electronic Systems Engineering degree from the Monterrey Institute of Technology (ITESM), Campus Toluca, Mexico in 1999 (with honors as the best score from all majors). Since the fall of 2000 he has been working towards the Ph.D. degree at Analog and Mixed-Signal Center (AMSC), Texas A&M University. During the spring and summer of 2000 he was a Design Engineer with Motorola Broadband Communications Sector. In the summer of 2002 he was with the Read Channel Design Group at Agere Systems where he investigated wide tuning range GHz LC VCOs for mass storage applications. During the summer of 2004 he was with the Mixed-Signal Communications IC Design Group at the IBM T. J. Watson Research Center, where worked on design and analysis of SiGe power amplifiers for millimeter wave radios. Since the fall of 2001 he has been a Semiconductor Research Corporation (SRC) research assistant at the AMSC working on the development of analog built-in testing techniques. Since the fall of 2000, Alberto has been the recipient of a scholarship from the Mexican National Council for Science and Technology (CONACYT). He represented Mexico in the 1994 Odyssey of the Mind World Creativity Contest and in the 1997 International Exposition for Young Scientists. His present research interests include built-in testing implementations for analog and RF circuits, system level design for wireless receivers and RF circuit design for UltraWideBand (UWB) communications.Jose Silva-Martinez was born in Tecamachalco, Puebla, México. He received the B.S. degree in electronics from the Universidad Autónoma de Puebla, México, in 1979, the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica (INAOE), Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autonoma de Puebla, where he remained until 1993; He was a co-founder of the graduate program on Opto-Electronics in 1992. From 1985 to 1986, he was a Visiting Scholar in the Electrical Engineering Department, Texas A&M University. In 1993, he re-joined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department; He was a co-founder of the Ph.D. program on Electronics in 1993. He is currently with the Department of Electrical Engineering (Analog and Mixed Signal Center) Texas A&M University, at College Station, where He holds the position of Associate Professor. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical application. Dr. Silva-Martinez has served as IEEE CASS Vice President Region-9 (1997–1998), and as Associate Editor for IEEE Transactions on Circuits and Systems part-II from 1997–1998 and May 2002–December 2003. Since January 2004 is serving as Associate Editor of IEEE TCAS Part-I. He was the main organizer of the 1998 and 1999 International IEEE-CAS Tour in region 9, and Chairman of the International Workshop on Mixed-Mode IC Design and Applications (1997–1999). He is the inaugural holder of the TI Professorship-I in Analog Engineering, Texas A&M University. He was a co-recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.Edgar Sánchez-Sinencio was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1966, 1970, and 1973, respectively. In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983-1984. He is currently the TI J Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE Trans. on Circuits and Systems, (1985–1987), and an Associate Editor for the IEEE Trans. on Neural Networks. He is the former Editor-in-Chief of the Transactions on Circuits and Systems II. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press 1999). In November 1995 he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico. The first honorary degree awarded for Microelectronic Circuit Design contributions. He is co-recipient of the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He was the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000–2002). He is presently a member of the IEEE Solid-State Circuits Fellow Award Committee. His present interests are in the area of RF-Communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member since 1992.     

A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz

A low power divide-by-8 injection-locked frequency divider is presented. The frequency divider consists of four current-mode logic (CML) D-latches connected in the form of a four-stage ring with the differential input signal injected into the clock terminals of the latches. The output signals can be taken from the data terminals of any of the four latches. The proposed frequency divider has higher operating frequency and lower power dissipation compared with conventional static frequency dividers. Compared with existing injection-locked frequency dividers, the proposed fully differential frequency divider presents wider locking range with the center frequency independent of injection amplitude. The frequency divider is implemented in TSMC 0.18 mum CMOS technology. It consumes around 3.6 mW power with 1.8 V supply. The operating frequency can be tuned from 4 GHz to 18 GHz. The ratio of the locking range over the center frequency is up to 50% depending on the operating frequency and biasing conditions     

Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band Gm–C Filters

A 330-MHz fifth-order G_m-C continuous-time low-pass filter with 24-dB boost is presented. Existing solutions are found to be unsuitable for low-power, wide-band, and high-boost operation. The proposed solution realizes two symmetric real axis zeros by efficiently combining transfer functions associated with all nodes of cascaded biquad cells. Application of Gilbert cell as a variable transconductor, for achieving constant parasitic capacitance across wide programmability range, is illustrated. A new common-mode feedback error amplifier that improves common-mode accuracy without compromising on bandwidth or circuit complexity is introduced. A prototype is fabricated in a standard 0.35-mum CMOS process. Experimental results show -41 dB of IM3 for 250-mV peak-peak swing with 43 mW of power dissipation     

A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner

A high dynamic range RF variable gain amplifier (RFVGA) suitable for mobile digital television (DTV) tuners is presented. Variable gain is achieved using a capacitive attenuator and current-steering transconductance (G_m) stages, which provide high linearity with relatively low power consumption. A novel broadband input impedance matching scheme based on resistive shunt-feedback is proposed. This scheme allows the RFVGA to achieve a low noise figure. A gain control technique suitable for CMOS current-steering variable gain amplifiers is described; it features 1 dB per step resolution, independent of process and temperature variations. The chip is fabricated in six-metal 0.18mum CMOS technology and consumes 12.2mA current from 1.8V supply. The RFVGA achieves 16dB maximum gain, 33dB gain control range, a 4.3dB noise figure, and an IIP3 higher than 25dBm