On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks

The impact of TiN film thickness variations on the effective work function (WF) of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON interfaces has been investigated. The electrical signatures of these gate stacks indicate that the concentration of Hf-Ti and Ti-Si bonds at the (poly-Si/TiN)/HfSiON and (poly-Si/TiN)/SiO/sub 2/ interface plays a significant role on the control of the gate stacks' WF. The density of these interfacial bonds and the related work function changes are correlated to the degree of nucleation of the TiN film on the dielectric.     

Effective Work-Function Modulation by Aluminum-Ion Implantation for Metal-Gate Technology (Poly-Si/TiN/SiO2)

The impact of aluminum (Al) implantation into TiN/SiO₂ on the effective work function (EWF) of poly-Si/ TiN/SiO₂ is investigated. Al implanted at 5 keV with a dose of 5 times 10¹⁵ cm^-2 reduces the flatband voltage (V_FB) and the EWF of poly-Si/TiN/SiO₂ stack by ~150 mV compared with the unimplanted poly-Si/TiN/SiO₂ stack. This reduction of V_FB is found to be dose-dependent, which is correlated to the Al concentration at the TiN-SiO₂ interface as evidenced by secondary-ion-mass-spectrometry profiles. The interface dipole created due to the Al presence at the metal-dielectric interface is believed to contribute to the observed V_FB (or EWF) reduction (or increase). This technique for EWF modulation is promising for further threshold-voltage (V_t) tuning without any process complexities and is quite significant for planar and multiple gate field-effect transistors on fully depleted silicon on insulator.     

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-/spl kappa/ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)/spl sim/50%) results in: 1) an increase of the effective work function by /spl sim/ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V/sub o/)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V/sub o/-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.     

Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: (a) deposition of a Dy₂O₃ capping layer on the host dielectric (SiON or HfSiON), or (b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: (1) both cases result in dielectric modification with gate leakage (J_G) reduction; (2) adding a cap has no significant impact on T_inv(<1 Å), while up to ～5 and 2 Å reduction occurs for SiON and HfSiON Yb-implanted devices, respectively, (3) the largest J_G reduction (150×) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in J_G and mobility but with 500 mV smaller V_T; (4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; (5) excellent process control and reliability behavior (V_T instability by a.c. pulsed IV, PBTI and TDDB) is reported for both eWF tuning methods. They allow ΔeWF(n?p) values up to ～800 meV when combined with Ni–silicide FUSI phase engineering, promising for low-V_T CMOS.     

Methodology for Flatband Voltage Measurement in Fully Depleted Floating-Body FinFETs

Among the novel methods for flatband voltage (V_fb) measurement, we demonstrate that a gate-leakage-based technique is the most suitable for measuring V_fb in floating-body MOSFETs with ultrathin gate dielectrics. Starting from carrier separation experiments on planar MOSFETs, we show the universality of the gate conduction mechanism dependence on band alignment for both n- and p-FETs. We demonstrate that metrics based on the gate leakage (either its valence-band electron-tunneling component or its first-order derivative) reflect this dependence and allow equivalent-oxide-thickness-independent V_fb quantification. This dependence is also valid for high-k and capped gate dielectrics, whereas their gate conduction mechanism is dominated by direct tunneling. To illustrate, we extract gate-leakage-derivative-based metrics and measure V_fb of TaN and TiN gate electrodes in multiple-fin FETs integrated on silicon-on-insulator.     

Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $hbox{Dy}_{2}hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics

This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy₂O₃ cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Aring Dy₂O₃ cap resulting in DeltaeWF ap 400 meV and final eWF ap 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Well-behaved short-channel devices ( Lg ~ 100 nm, SS ~ 70 mV/dec, and DIBL ~ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy₂O₃ cap (5 Aring)] devices with NiSi-FUSI gates, corresponding to a similar . This capping approach, when combined with Ni-silicide FUSI phase engineering, allows (n-p) values up to 800 meV, making it promising for low- CMOS.     

Electrical Properties of nMOSFETs Using the NiSi:Yb FUSI Electrode

In this letter, nMOSFETs using a NiSi:Yb fully silicide (FUSI) electrode are demonstrated for the first time. We report that the integration of NiSi:Yb FUSI into our reference n-FETs with the respective SiON / HfSiON gate dielectrics results in a V_t reduction from 0.55/0.52 down to 0.30/0.43 V, without degradation of the gate dielectric integrity, channel interface states, and long channel device mobility