排序方式: 共有3条查询结果,搜索用时 78 毫秒
1
1.
2.
Parthasarathy N. Griffith Z. Kadow C. Singisetti U. Rodwell M.J.W. Xiao-Ming Fang Loubychev D. Ying Wu Fastenau J.M. Liu A.W.K. 《Electron Device Letters, IEEE》2006,27(5):313-316
This letter reports InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBTs) employing an N/sup +/ subcollector and N/sup +/ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C/sub cb/ associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N/sup +/ subcollector that lies underneath the base ohmic contact, as well as compensate the /spl sim/1-7/spl times/10/sup -7/ C/cm/sup 2/ surface charge at the interface between the indium phosphide (InP) substrate and the N/sup $/collector drift layer. By implanting the subcollector, C/sub cb/ associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C/sub cb/ by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f/sub /spl tau// and 403-GHz f/sub max/. The dc current gain /spl beta//spl ap/38, BV/sub ceo/=6.0 V, BV/sub cbo/=5.4 V, and I/sub cbo/<50 pA at V/sub cb/=0.3 V. 相似文献
3.
Singisetti U. Wistey M.A. Burek G.J. Baraskar A.K. Thibeault B.J. Gossard A.C. Rodwell M.J.W. Byungha Shin Kim E.J. McIntyre P.C. Bo Yu Yu Yuan Wang D. Yuan Taur Asbeck P. Yong-Ju Lee 《Electron Device Letters, IEEE》2009,30(11):1128-1130
Abstract-We report Al2O3Zln0.53Ga0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n+ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In0.53Ga0.47As channel with an In0.4sAl0.52As back confinement layer and the n++ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed ID = 0.95 mA/mum current density at VGS = 4.0 V and gm = 0.45 mS/mum peak transconductance at VDS = 2.0 V. 相似文献
1