X-Align: Improving the Scan Cell Observability of Response Compactors

While response compaction reduces the size of expected vectors that need to be stored on tester memory, the consequent information loss inevitably reflects into loss in test quality. Unknown x's further exacerbate the quality loss problem, as they mask out errors captured in other scan cells in the presence of response compactors. In this paper, we propose a technique that manipulates the x distribution in scan responses prior to their propagation into the response compactor. A block, which we refer to as x-align, inserted between the scan chains and the response compactor aligns response x's within the same slices as much as possible in order to increase the number of scan cells that can be observed through the compactor. The alignment of x's is achieved by delaying the scan-out operations in the scan chains, wherein the proper delay values are computed judiciously. We present an Integer Linear Programming (ILP) formulation and a computationally efficient greedy heuristic for the computation of the delay values for scan chains. The x-align hardware is generic yet reconfigurable. An analysis of x distribution in a captured response helps compute the proper delay values, with which x-align is reconfigured to maximize the alignment of x's. The scan cell observability enhancement delivered by x-align paves the way for the utilization of simple response compactors, such as parity trees, yet providing high levels of test quality even in the presence of a large density of response x's. X-align can also be utilized with any response compactor to manipulate the x distribution in favor of the compactor, thus improving the test quality attained.     

Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires

We introduce a logic-level soft error mitigation methodology for combinational circuits. The proposed method exploits the existence of logic implications in a design, and is based on selective addition of pertinent functionally redundant wires to the circuit. We demonstrate that the addition of functionally redundant wires reduces the probability that a single-event transient (SET) error will reach a primary output, and, by extension, the soft error rate (SER) of the circuit. We discuss three methods for identifying candidate functionally redundant wires, and we outline the necessary conditions for adding them to the circuit. We then present an algorithm that assesses the SET sensitization probability reduction achieved by candidate functionally redundant wires, and selects an appropriate subset that, when added to the design, minimizes its SER. Experimental results on ISCAS'89 benchmark circuits demonstrate that the proposed soft error mitigation methodology yields a significant SER reduction at the expense of commensurate hardware, power, and delay overhead.     

On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power

Scan-based testing of integrated circuits results in significant switching activity during the shift operations, dissipating excessive power levels. When such levels are beyond the peak power level under which the chip can functionally operate at, it may lead to an unexpected behavior of the design, resulting in a yield loss. One of the most effective solutions to reduce peak shift power is to partition the scan chains into multiple groups, wherein a single group is active at any time instance within a shift cycle. The partitioning of the chains into groups can be performed statically, i.e., per test set, or dynamically, i.e., per test pattern. In this work, we address the application of dynamic scan chain partitioning for reducing peak shift power. First, we address the application of dynamic partitioning to test delay faults in at-speed test techniques. Then, we formulate the scan chain partitioning problem via Integer Linear Programming (ILP), in order to evenly distribute the transitions produced by any pattern over multiple time instances within the shift cycle, maximally reducing the peak shift power. Finally, we evaluate the power reduction benefit of dynamic partitioning through an extensive set of experiments using different scan configurations and test set characteristics of benchmark circuits as well as industrial designs. The results indicate that dynamic partitioning provides significant reduction to peak shift power over static partitioning methods, and that the benefit is accentuated in scan architectures with fewer scan chains, test sets with more don’t care bits, and designs with larger variances of weight differences for transitions in the scan cells.     

Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints

Concurrent Error Detection (CED) methods provide some level of error detection capability at the cost of some area and power overhead. Incorporating CED schemes into Integrated Circuits (ICs) is becoming increasingly more important, as the continuous technology scaling leads to an ever-higher transient error-related failure rate. For many applications, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for ICs. While duplication provides high CED coverage, its power budget requirement of having two circuits operate all the time limits its application. The key idea of reconfiguration is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using random and judicious selection of control conditions indicate that power dissipation is commensurate with CED coverage, supporting the use of LFSR structures to easily generate and adjust conditions dynamically to adapt to the power constraints of the system during its operation. Moreover, online testing using nonidentical input vectors can also be incorporated, improving the tradeoff between power dissipation and CED coverage.     

Compaction-based concurrent error detection for digital circuits

We present a non-intrusive concurrent error detection (CED) method for combinational and sequential digital circuits. We analyze the optimal solution model and point out the limitations that prevent logic synthesis from yielding a minimal-cost monolithic CED implementation. We then propose a compaction-based alternative approach for restricted error models. The proposed method alleviates these limitations by decomposing the CED functionality into: compaction of the circuit outputs, prediction of the compacted responses, and comparison. We model the fault-free and erroneous responses as connected vertices in a graph and perform graph coloring in order to derive the compacted responses. The proposed method is first discussed within the context of combinational circuits, with zero detection latency, and subsequently extended to Finite State Machines (FSMs), with a constant detection latency of one clock cycle. Experimental results demonstrate that the proposed method achieves significant hardware reduction over duplication-based CED, while detecting all possible errors.