A modified advancing layers mesh generation for thin three-dimensional objects with variable thickness

A method of generating modified advancing layers mesh is proposed. In this paper the mesh generation process of semi-unstructured prismatic/tetrahedral mesh is presented for relatively thin three-dimensional geometries with variable thickness, as in the case of injection molding analysis. Prismatic meshes are generated by offsetting initial surface triangular meshes. During the mesh generation process, mesh quality is efficiently improved with the use of a new node relocation method. Finally, tetrahedral meshes are automatically generated in the rest of the domain. The mesh generating capability of the proposed algorithm is demonstrated with the several practical test cases.     

Full software analysis and impedance matching of radio frequencyCMOS integrated circuits

We present a systematic analysis technique of complementary metal-oxide-semiconductor (CMOS) radio-frequency (RF) integrated circuits (ICs). A full simulation program with integrated circuit emphasis (SPICE) simulation of the whole chip including the package and the die, with the parameters extracted from purely software analysis, has been performed. It is shown that the RF impedance matching without S-parameter based techniques is possible and the measured results agree well with our SPICE-only software based technique     

Bias-heating recovery of MWCNT gas sensor

A sensor was made using Au/Cr electrodes on a glass substrate and a thin carbon multiwall nanotube film printed between them. A bias-heating method was used completely to desorb gas molecules and restore its initial conductance. The temperature of the thin carbon nanotube film varied depending on the magnitude of the voltage used, and this relationship was investigated. After being used to detect NO₂, the sensor returned to its initial conductance. This method enables complete recovery without additional processing steps, such as the fabrication of heat structure and ambient heating.     

Quadrilateral mesh generation on trimmed NURBS surfaces

An automatic mesh generation scheme with unstructured quadrilateral elements on trimmed NURBS surfaces has been developed. In this paper NURBS surface geometries in the IGES format have been employed to represent geometric models. For unstructured mesh generation with quadrilateral elements, a domain decomposition algorithm employing loop operators has been modified. As for the surface meshing, an indirect 2D approach is proposed in which both quasi-expanded planes and projection planes are employed. Sample meshes for complex models are presented to demonstrate the robustness of the algorithm.     

3D welding and milling: part II—optimization of the 3D welding process using an experimental design approach

A process of combined additive and subtractive techniques for the direct freeform fabrication of metallic prototypes and tools is being developed by the authors. This hybrid process, called ‘3D welding and milling’, uses gas metal arc welding (GMAW) as an additive and conventional milling as a subtractive technique, thereby exploiting the advantages of both processes. In this paper, the results of the optimization of the deposition process using a statistical approach as well as the result of plastic injection molding with the inserts fabricated by this hybrid process are described. The result proves the applicability of the 3D welding and milling process for direct fabrication of metallic prototypes and tools.     

Simplified evaluation criterion for concepts of engineering design based on cost,simplicity, and safety

Journal of Mechanical Science and Technology - In the early stages of engineering design, numerous concepts may be envisioned and suggested. Considering normal time constraints, a large degree of...     

Current-mode cyclic ADC for low power and high speed applications

A new current-mode cyclic ADC is proposed. An 8 bit ADC is fabricated and fully tested. The experimental results are summarised and compared with other schemes. This ADC enables a conversion time less than 10 mu s with clock frequency of 450 kHz to be obtained. The proposed ADC is found to be useful where the power and size are crucial requirements.<>     

Search for a new design of deburring tools for intersecting holes with TRIZ

This work describes a process of design improvement of deburring tools for intersecting holes based on the TRIZ approach. Deburring tests with the previous deburring tool prototypes showed surface irregularity on the deburred edges. The irregularity is due to the complex interaction, governed by various parameters, between the cutter head and the three-dimensional burr edge. The major parameters affecting the tool dynamics are identified and contradiction analysis of TRIZ is performed for the problem. Among the several candidate solution principles, “asymmetry” is adopted for the new design. With the new design based on this principle of asymmetry, variations in the rake angle and cutter face exposure are greatly reduced. Tests on aluminum alloy Al6061-T6 specimens showed significantly less surface irregularity. An index of surface irregularity is proposed.     

Unstructured tetrahedral meshing by an edge-based advancing front method

This paper proposes an unstructured tetrahedral meshing algorithm for CAD models in the IGES format. The work presented is based on the advancing front method, which was proposed by the third author. Originally, the advancing front method uses three basic operators, namely, trimming, wedging, and digging. In this research, in addition to the basic operators, three new operators splitting, local finishing, and octahedral-are added to stabilize the meshing process. In addition, improved check processes are applied to obtain better-shaped elements. The algorithm is demonstrated and evaluated by four examples.     

High performance CMOS current comparator using resistive feedbacknetwork

A new high speed, low power and small area CMOS current comparator based on a resistive feedback network is proposed. Simulation results employing 0.35 μm CMOS parameters demonstrate 7 ns response time and 0.45 mW power consumption for 0.1 μA input current, which represents a ~400% improvement in power-delay product over existing current comparators. In this design, the bias current and the input impedance are well controlled parameters, and the inherent autozeroing scheme does not require any offset compensation