Multilevel-spiral inductors using VLSI interconnect technology

A multilevel-spiral (MLS) inductor structure for implementation in VLSI interconnect technology is presented. Inductances of 8.8 and 32 nH and maximum quality-factors (Q) of ~6.8 and 3.0, respectively, are achieved in a four-level metal BiCMOS technology, with four turns at each of the two or four stacked spiral coils and with an area of 226×226 μm². The comparison of the MLS inductors to different single-level-spiral (SLS) control devices shows that a MLS inductor provides the same inductance at ~50% dc resistance, but the maximum Q is typically measured at a lower frequency and the self-resonance frequency is reduced due to a high inter-wire capacitance     

Multilevel monolithic inductors in silicon technology

Multilevel monolithic inductors implemented in standard BiCMOS technology are presented. Use of top metal layers shunted with vias provides Q values approaching 10 at 2.4 GHz and above 6 at 900 MHz for a 2 nH inductor. There is no modification to the conventional wiring metallurgy and no need for extra processing steps     

An 11 GHz 3-V SiGe voltage controlled oscillator with integratedresonator

A 10.5- to 11-GHz fully monolithic voltage controlled oscillator circuit implemented in a standard SiGe bipolar technology is presented. An oscillator phase noise of -78 to -87 dBc/Hz is achieved at 100-kHz offset. The tuning range is close to 5% with an on-chip varactor-tuned resonator and for a control voltage of 0 to 3 V. The circuit draws less than 8 mA from a 3-V supply including the reference branch bias current     

Single-chip 4×500-MBd CMOS transceiver

A CMOS chip containing four 500-MBd serializer/deserializer pairs has been designed to relieve interconnect congestion in an ATM switch system. The 9.7×9.7 mm² chip fabricated in a 0.8-μm technology is packaged on a ceramic ball grid array and dissipates 3.5 W. It replaces a 72-wire parallel interface with an eight-line serial interface transparent to the user and supports transmission at 1.6 Gb/s per direction in full-duplex mode. Virtually error-free operation in a system environment over electrical serial links having up to 9 dB loss at 500 MHz has been realized using signal predistortion for the serial bit stream and PLL clock recovery for each of the four receivers. Interface timing and serial-link driver strength are programmable     

Integrated RF components in a SiGe bipolar technology

Several components for the design of monolithic RF transceivers on silicon substrates are presented and discussed. They are integrated in a manufacturable analog SiGe bipolar technology without any significant process alterations. Spiral inductors have inductance values in the range of ~0.15-80 nH with typical maximum quality-factors (Q_max ) of 3-20. The Q_max's are highest if the doping concentration under the inductors is kept minimum. It is shown that the inductor area is an important parameter toward optimization of Q_max at a given frequency. The inductors can be represented in circuit design by a simple lumped-element model. MOS capacitors have Q's of ~20/f (GHz)/C(pF), metal-insulator-metal (MIM) capacitors reach Q's of ~80/f (GHz)/C(pF), and varactors with a 40% tuning range have Q's of ~70/f (GHz)/C(pF). Those devices can he modeled by using lumped elements as well. The accuracy of the modeling is verified by comparing the simulated and the measured high-frequency characteristics of a fully integrated, passive-element bandpass filter     

A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit insilicon bipolar technology

A monolithic clock and data recovery PLL circuit is implemented in a digital silicon bipolar technology without modification. The only external component used is the loop filter capacitor. A self-aligned data recovery architecture combined with a novel phase-detector design eliminates the need for nonlinear processing and phase shifter stages. This enables a simpler design with low power and reduced dependence on the bit rate. At 2.3 Gb/s, the test chip consumes 100 mW from a -3.6-V supply, excluding the input and output buffers. The worst-case rms jitter of the recovered clock is less than 14 ps with 2²³-1 pseudorandom bit sequence     

RF circuit design aspects of spiral inductors on silicon

The design and optimization of spiral inductors on silicon substrates, the related layout issues in integrated circuits, and the effect of the inductor-Q an the performance of radio-frequency (RF) building blocks are discussed. Integrated spiral inductors with inductances of 0.5-100 nH and Q's up to 40 are shown to be feasible in very-large-scale-integration silicon technology. Circuit design aspects, such as a minimum inductor area, the cross talk between inductors, and the effect of a substrate contact on the inductor characteristics are addressed. Important RF building blocks, such as a bandpass filter, low-noise amplifier, and voltage-controlled oscillator are shown to benefit substantially from an improved inductor-Q     

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P_1dB of 10 to 12dBm, P_sat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated     

A 2.4-GHz silicon bipolar oscillator with integrated resonator

A 2.4 GHz fully-monolithic silicon-bipolar oscillator circuit implemented in a 12 GHz BiCMOS technology is presented. The integrated resonator circuit uses three different versions of a 2 nH multilevel inductor and a wideband capacitive transformer. The measured Q factor is 9.3 for the three-level inductor. An oscillator phase noise of -78 dBc/Hz is achieved at 20 kHz offset. The circuit dissipates 50 mW from a 3.6 V supply     

Frequency limitations of a conventional phase-frequency detector

The phase and frequency discriminator characteristics of a digital phase-frequency detector (DPFD) are analyzed in detail. Analytical expressions that correctly predict the high-frequency behavior of the circuit are derived. The results show excellent agreement with measurements and computer simulations