A 12-Bit, 10-MHz Bandwidth, Continuous-Time $SigmaDelta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 mum times 660 mum. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SigmaDelta ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.     

Graphics Standards: The Pace Quickens

In recent months the pace of standards development for computer graphics has quickened. One standard has been adopted, accepted, and has already demonstrated its effectiveness. Another has now achieved the status of Draft International Standard, and is becoming an American National Standard as well. Several companies have made public announcements of their support for standards, and there has been extensive press coverage. This paper shall attempt to place all of this activity in perspective.     

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 mum integrated circuits, which have a combined active area of 0.06 mm² and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.     

The standardization of three-dimensional graphics systems

This paper is intended to provide a status report on the development of standards for three-dimensional computer graphics. A model is developed for the general problem of extension of a computer system to a more general case than that for which it was originally designed. The model is then applied to the standardization of computer graphics.