Reverse short channel effects in high-k gated nMOSFETs

Anomalous threshold voltage roll-up behavior, commonly referred as reverse short channel effect (RSCE), has been observed in high-k (HfO₂ on SiON buffer, Al₂O₃ on SiON buffer) gated submicron nMOSFETs, while the SiO₂ or SiON control samples show normal short channel effect (SCE) behavior. The possible causes such as inhomogeneous channel doping profile and gate oxide thickness variation near S/D ends have been ruled out. The results indicate that interface trap density that dependents on channel length is the main cause of the RSCE observed here. In addition, oxide charge also plays a role.     

Ohmic contacts to semiconducting diamond using a Ti/Pt/Au trilayer metallization scheme

Ohmic contacts have been fabricated on a naturally occurring type IIb diamond crystal using an annealed Ti/Pt/Au trilayer metallization where the Pt served successfully as a barrier to Ti diffusion into the Au capping layer. However, a specific contact resistance could not be reliably determined using transmission line model measurements. Auger microanalysis revealed the presence of Ti on the diamond surface near the ohmic contact pads. The most likely origin of the Ti on the diamond surface was determined to be lateral diffusion from beneath the contact pads. This would have produced a nonuniform concentration of Ti across the diamond surface which, in turn, would have affected the diamond sheet resistance in a complicated way.     

Detailed study and projection of hard breakdown evolution in ultra-thin gate oxides

The mechanism responsible for post-soft breakdown leakage current increase in ultra-thin oxides depends on the nature of the conducting filament formed at the instant of dielectric breakdown. The conductance of the filament formed during soft breakdown has been observed to be either stable until hard breakdown occurs or to increase continually with time. The acceleration factors for predicting hard breakdown are different in each case. Recent experimental results suggest that the “hardness” of the first breakdown influences the type of conducting filament formed during the soft breakdown event the time in which hard breakdown subsequently occurs. Electron current-induced defect formation appears to be the driving force for the eventual hard breakdown event.     

A monolithic CMOS microhotplate-based gas sensor system

A monolithic CMOS microhotplate-based conductance-type gas sensor system is described. A bulk micromachining technique is used to create suspended microhotplate structures that serve as sensing film platforms. The thermal properties of the microhotplates include a 1-ms thermal time constant and a 10/spl deg/C/mW thermal efficiency. The polysilicon used for the microhotplate heater exhibits a temperature coefficient of resistance of 1.067/spl times/10/sup -3///spl deg/C. Tin(IV) oxide and titanium(IV) oxide (SnO/sub 2/,TiO/sub 2/) sensing films are grown over postpatterned gold sensing electrodes on the microhotplate using low-pressure chemical vapor deposition (LPCVD). An array of microhotplate gas sensors with different sensing film properties is fabricated by using a different temperature for each microhotplate during the LPCVD film growth process. Interface circuits are designed and implemented monolithically with the array of microhotplate gas sensors. Bipolar transistors are found to be a good choice for the heater drivers, and MOSFET switches are suitable for addressing the sensing films. An on-chip operational amplifier improves the signal-to-noise ratio and produces a robust output signal. Isothermal responses demonstrate the ability of the sensors to detect different gas molecules over a wide range of concentrations including detection below 100 nanomoles/mole.     

Investigation of the intrinsic SiO2 area dependence using TDDB testing and model integration into the design process

This paper models the area dependency for thin SiO₂ films (1.2E-7 to lE-2 cm²) using Time Dependent Dielectric Breakdown testing over a wide range of electric fields and test temperatures. The data generated indicates that the field and temperature acceleration factors are the same for all the areas tested indicating that the failure mechanism is the same even though the times to failure are different for all the area sizes. The paper will explain and model the area effect on TDDB lifetime and use the model to predict gate oxide reliability in the design cycle.     

Ultrathin gate oxide reliability: physical models, statistics, andcharacterization

The present understanding of wear-out and breakdown in ultrathin (t_ox < 5.0 nm) SiO₂ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed     

Asymmetric energy distribution of interface traps in n- and p-MOSFETs with HfO/sub 2/ gate dielectricon ultrathin SiON buffer layer

The variable rise and fall time charge-pumping technique has been used to determine the energy distribution of interface trap density (D/sub it/) in MOSFETs with a HfO/sub 2/ gate dielectric grown on an ultrathin (<1 nm)-SiON buffer layer on Si. Our results have revealed that the (D/sub it/) is higher in the upper half of the bandgap than in the lower half of the bandgap, and are consistent with qualitative results obtained by the subthreshold current-voltage (I--V) measurements, capacitance-voltage (C-V), and ac conductance techniques. These results are also consistent with the observation that n-channel mobilities are more severely degraded than p-channel mobilities when compared to conventional MOSFETs with SiO/sub 2/ or SiON as the gate dielectric.     

A new technique for determining long-term TDDB accelerationparameters of thin gate oxides

A new technique, the dual voltage versus time curve (V-t) integration technique, is presented as a much faster method to obtain time-dependent dielectric breakdown (TDDB) acceleration parameters (α and τ) of ultrathin gate oxides compared to conventional long-term constant voltage stress tests. The technique uses V-t curves measured during highly accelerated constant or ramped current injection breakdown tests. It is demonstrated that the technique yields acceleration parameters that are statistically identical to values obtained from long-term constant voltage TDDB tests. In contrast to traditional TDDB tests, the proposed technique requires over an order of magnitude less testing time, a smaller sample size, and can be used during production monitoring     

Reliability of laser-induced metallic vertical links

A new method has been proposed to form electrical connections vertically between two levels of metallization by using a commercial pulsed IR laser system. Samples were stressed at accelerated current densities and temperatures. The failure activation energy has been found to be about 0.66 eV, from which electromigration is identified as a main failure mode. The extrapolated mean time to failure (MTTF) at room temperature and accelerated current density of 3 MA/cm² is about 38 years. The dependence of MTTF on laser energy has also been obtained, showing agreement with the resistance dependence on laser energy. Focused ion beam (FIB) cross sections suggest that the laser process-induced voids in the lower line limit the lifetime of links. Furthermore, a modified structure is proposed to improve the electromigration reliability. From the reliability point of view, this study shows that the laser-induced vertical link has sufficient reliability for practical implementation     

Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells

We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memory with HfO(2) charge trapping layers of varying thicknesses. The memory cells, which are fabricated by self-aligning in situ grown Si nanowires, exhibit high performance, i.e. fast program/erase operations, long retention time and good endurance. The effect of the trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO(2) increases from 5 to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. These data indicate that the electric field across the tunneling oxide is not affected by HfO(2) thickness, which is in good agreement with simulation results. Our work also shows that the Omega gate structure improves the program speed and retention time for memory applications.