A method for locating fault section by using sequential information at substations

This paper presents a new real-time method for locating fault section at substations. When a fault occurs, considerable information resulting from protective relay operation and circuit-breaker operation is recorded. Using this information an attempt is made to locate the fault section, especially by considering the sequential relationship of the information and by dividing fault areas. Primarily, in this method, the fault area is divided into several sections based on protection area and operation time of protective relays. Next, expecting subsequent operation of backup relays, the “waiting time” for reasoning is given to each divided section. After a lapse of “waiting time,” all the suspected fault sections are extracted and given priority based on the empirical knowledge of experts. A prototype of the expert system was developed for fault section location, which was applied to various complicated fault cases. The effectiveness of the method was proved even in case of multiple faults and no-operation of protective relays the circuit breakers.     

A functional MOS transistor featuring gate-level weighted sum andthreshold operations

A functional MOS transistor is proposed which works more intelligently than a mere switching device. The functional transistor calculates the weighted sum of all input signals at the gate level, and controls the `on' and `off' of the transistor based on the result of such a weighted sum operation. Since the function is quite analogous to that of biological neurons, the device is named a neuron MOSFET, or neuMOS (vMOS). The device is composed of a floating gate and multiples of input gates that capacitively interact with the floating gate. As the gate-level sum operation is performed in a voltage mode utilizing the capacitive coupling effect, essentially no power dissipation occurs in the calculation, making the device ideal for ULSI implementation. The basic characteristics of neuron MOSFETs as well as of simple circuit blocks are analyzed based on a simple transistor model and experiments. Making use of its very powerful function, a number of interesting circuit applications are explored. A soft hardware logic circuit implemented by neuMOS transistors is also proposed     

Pressure-induced tin whisker formation

This paper presents a fundamental assessment of pressure-induced tin whisker formation. A creep-based tin whisker model was developed to explain experimental data as well as data from industrial studies. A grain boundary diffusion model was then developed to predict a maximum whisker length. It is shown that creep properties obtained from samples can be used to screen plating finishes susceptible to tin whiskering. This enables a manufacturer to assess tin whisker risks prior to volume production.     

Intelligence implementation on silicon based on four-terminal device electronics

We will propose the concept of a “four-terminal device” which functionally surpasses three-terminal devices like MOSFET's and bipolar transistors in the ability of controlling the current flowing through a device. The enhanced functionality at the very elemental transistor level is quite essential in creating intelligent functions at the system level. A neuron MOSFET (νMOS), a multiple-input-terminal floating-gate device, is taken as an example of a four-terminal device and the implementation of new-architecture electronic circuits is demonstrated. The binary-multivalue-analog merged hardware algorithms conducted by vMOS circuits provide a highly flexible data processing scheme while assuring the accuracy of binary digital computation, thus presenting a very promising approach to implementing human-intelligence electronic systems on silicon.     

Neuron MOS binary-logic integrated circuits. I. Design fundamentalsand soft-hardware-logic circuit implementation

Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor (νMOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage νMOS inverters. One of the most striking features of νMOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified     

Catalytic Performance of Aged Rh/CeO2–ZrO2 for NO–C3H6–O2 Reaction Under a Stoichiometric Condition

The activity of Rh/CeO₂ for NO reduction by C₃H₆ was gradually deceased by mixing with ZrO₂ until 68 mol%. Rh supported on CeO₂–ZrO₂ with higher OSC was found to show lower catalytic activity. High OSC of CeO₂–ZrO₂ would probably stabilize the surface of Rh in oxidized state, resulting in low activity and low efficiency of C₃H₆ utilization for NO reduction. In situ FT-IR spectroscopy suggested that mononitrosyl species such as Rh(NO)^δ? and Rh(NO)^δ+ are reaction intermediates in the NO–C₃H₆–O₂ reaction over Rh/CeO₂–ZrO₂ catalysts.     

Decomposition characteristics of biodegradable plastics made from sago starch‐extraction residue

Biodegradable plastics were synthesized for the effective use of sago starch‐extraction residue, which has been discarded as a waste. Two types of esterified sago starch‐extraction residue, P‐SP and L‐SP, were obtained. It had black color for P‐SP₁₆₀ (esterified by palm oil) to light yellow color for L‐SP₈₀ (esterified by lauric acid) and showed high carbon content, ranging from 399.3 to 537.1 g kg⁻¹. Biodegradable plastics from the residue, which had high esterification degree showed thermoplasticity and slower decomposition in Andisols in Japan and Inceptisols in Philippines. The esterification degrees of P‐SP₁₆₀ and L‐SP were 3.23 and 2.95 to 5.18 mmol g⁻¹, respectively. In addition, L‐SP₈₀ exhibited the most appropriate thermal softening behavior by heating. The cumulative decomposition of P‐SP₁₆₀ in Andisols and Inceptisols showed 16.7 and 32.8% of total carbon during 31 day of the incubation. On the other hand, the decomposition rates of L‐SP₈₀ in Andisols and Inceptisols were less than 10% of total carbon during 31 day of the incubation. The addition of triacetin as plasticizer to P‐SP₁₆₀ and L‐SP₈₀ remarkably influenced the decomposition rate of both molded P‐SP₁₆₀ and L‐SP₈₀. © 2010 Wiley Periodicals, Inc. J Appl Polym Sci, 2011     

Aqueous solution properties of disulfide-linked fluorinated gemini and cleaved monomeric thiol surfactants

We prepared a fluorinated gemini surfactant containing a disulfide bond in its spacer chain, [C?F??(CH?)?N(CH?)?CH?CH?SSCH?CH?N(CH?)?(CH?)?C?F??]2Cl, and its analogue with a hexamethylene spacer. Monomeric thiol surfactant, [C?F??(CH?)?N(CH?)?CH?CH?SH]Cl, was readily produced by the cleavage of the gemini surfactant using dithiothreitol in water. The critical micelle concentration was determined using surface tension, conductivity, and fluorescence probe methods. The critical micelle concentration of the monomeric surfactant was significantly larger than that of the gemini surfactant. The surface tension of aqueous solution for the cleaved monomeric thiol surfactant returned gradually to the original value through the formation of the disulfide bond via air oxidation.     

Development on a coaxial heat integrated distillation column (HIDiC)

Various configurations of a column for performing the principle of HIDiC can be proposed, but a coaxial column which is installed a packing in an inside tube and outer side may be one of the simplest columns for HIDiC. In order to examine whether or not the configuration of the packed column mentioned above is appropriate to HIDiC, an experimental apparatus has been set up and heat and mass transfer rates have been measured by using benzene-toluene system. This paper was presented at The 5th International Symposium on Separation Technology-Korea and Japan held at Seoul between August 19 and 21, 1999.     

An Approximation for the Production Efficiency of Automatic Transfer Lines with In-Process Storages

This paper considers the production efficiency of automatic transfer lines where in-process storages are provided for stochastic station breakdowns. A simple approximation method is developed in order to readily obtain the production efficiency and show the benefit of providing storages even for long lines. Additionally, the optimal partitioning of the line and the method of allocating capacities for storages are numerically investigated.