Dual-Band LC VCO Architecture With a Fourth-Order Resonator

A dual-band LC voltage-controlled oscillator (VCO) architecture suitable for GSM/PCS/DCS applications is presented. The VCO utilizes a fourth-order resonance tank and avoids quality-factor-deteriorating switches. The paper outlines the design tradeoffs and the VCO when using a fourth-order resonator. The 0.8-GHz/1.8-GHz test chip was fabricated in the 0.5-mum IBM-5AM SiGe process and has achieved phase noise of -134 dBc/Hz at a 1-MHz frequency offset from the carrier, with 56-MHz and 121-MHz tuning ranges in the corresponding bands. The VCO core consumes 15 mW from a 2.5-V power supply     

System- and circuit-level optimization of PLL designs for DVB-T/H receivers

This article proposes a framework for the optimization of voltage-controlled oscillator (VCO) designs in frequency synthesizers for digital video broadcasting ?C terrestrial/handheld (DVB-T/H) receivers. Linear time-invariant phase-domain model of a charge-pump phase-locked loop (PLL) is devised and includes both flicker (1/f) and thermal noise contributions from the loop oscillators. By modeling the entire receiver, it is shown that there are combinations of flicker and thermal noise contributions that result in a constant sum of inter-carrier interference (ICI) and adjacent channel interference, and constant symbol error rate as well. Consequently, optimization of the VCO phase noise spectrum is defined while maintaining the standard-specified symbol-error rate. Link-level performance evaluation is carried out to validate the stipulated trade-off. The effect of ICI mitigation schemes is discussed. Circuit-level VCO design approaches utilizing the derived trade-off are finally presented. The proposed optimization procedure is generic and is also applicable to other systems based on Orthogonal Frequency-Division Multiplexing.     

Semi-symbolic analysis (SSA) for amplitude control design of series resonance low-voltage VCO

The effect of an amplitude diode limiter on the oscillating conditions and frequency of oscillation of a 2.7 GHz series resonance LC-VCO, designed on Spectre-Cadence and implemented on 0.25 /spl mu/m BiCMOS process of Bell Labs, Lucent Microelectronics, is analysed by semi-symbolic analysis (SSA). The results show the value of the diode dynamic resistance needed and the resulting changes in the oscillating frequency.     

Evaluation and comparison of GHz‐range LC oscillators using time‐varying root‐locus

This paper presents a comprehensive comparison between complementary metal‐oxide‐semiconductor (CMOS) LC‐oscillator topologies often used in GHz‐range transceivers. The comparison utilizes the time‐varying root‐locus (TVRL) method to add new insights into the operation of different oscillators. The paper focuses on the treatment of the TVRL trajectories obtained for different oscillators and establishes links between the trajectories and physical phenomena in oscillators. The evaluation of the root trajectories shows the advantages of the TVRL method for comparing oscillator topologies, which is also extended towards the analysis of voltage‐controlled oscillators. The necessary circuit simplifications required in closed‐form root‐locus analysis are avoided by the TVRL, which allows precise oscillator comparison and reveals details on the topology specifics. The derived conclusions have been verified by the Cadence Spectre‐RF simulator on 130‐nm CMOS process. Copyright © 2011 John Wiley & Sons, Ltd.     

Technique for Flicker Noise Up-Conversion Suppression in Differential LC Oscillators

A novel technique for the suppression of the flicker noise up-conversion in a differential LC oscillator topology is proposed. Relaxation mechanism and tunable noise filtering of the relaxation thresholds provide simultaneous suppression of differential pair and bias transistor flicker noise contributions. The proposed technique is validated on a fully monolithic oscillator architecture and 0.35-mum standard CMOS process by Cadence SpectreRF for the frequency range of 2.9-5.9 GHz. The phase noise improvement at 10 kHz offset versus a single-differential-pair LC oscillator is 6-15 dB across the tuning range.     

A 4.3-GHz VCO with 2-GHz tuning range and low phase noise

A voltage-controlled oscillator (VCO) based on double cross-coupled multivibrator structure with a center frequency of 4.3 GHz and a tuning range of 2 GHz has been designed and implemented in standard 0.35 μm BiCMOS technology. The measured phase noise is 113 dBc/Hz at 600-kHz offset frequency from the carrier. The VCO draws 14.6 mA from the 2.5-V supply     

Monolithic RF bandpass track-and-hold

A new bandpass track-and-hold (BP-T/H) open loop architecture is developed as a single stage monolithic circuit with low voltage power supply. The sampling of 912 MHz RF-signal with 100 MS/s is demonstrated by Spectre-Cadence-4.4.6 simulations on 0.35 /spl mu/m RF-SiGe/BiCMOS process of Texas Instruments.     

1.2 V gigahertz-resonance-ring ICO/VCO

A new monolithic ring-oscillator-core is presented that is faster; requires a lower voltage power supply for a larger output amplitude at higher frequencies, and is simpler to control. Using low-Q inductors on 0.8 μm BiCMOS technology (17 GHz NPN) the resonance-ring ICO/VCO develops 3×9 GHz with 800 mV amplitude, from only 1.2 V and 5.4 mW with a control ability of 100 MHz/mA. The phase noise is expected to be <-100 dBc/Hz. The circuit is suitable for very-high-speed communications and computer applications     

Evaluating parallel architectures for two real-time applicationswith 100 kHz repetition rate [hadron collider data]

In the context of research and development activities for future hadron colliders, competitive implementations of real-time algorithms for feature extraction have been made on various forms of commercial pipelined and parallel architectures. The algorithms used for benchmarking serve for decision making and are of relative complexity; they are required to run with a repetition rate of 100 kHz on data sets of kilobyte size. Results are reported and discussed in detail. Among the commercially available architectures, pipelined image processing systems can compete with custom-designed architectures. General-purpose processors with systolic mesh connectivity can also be used. Massively parallel systems of the SIMD type (many processors executing the same program on different data) are less suitable in the presently marketed form