Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In_0.3Ga_0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications     

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In_0.7Ga_0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system     

Characteristics of GdGaO grown by MBE

Ga₂O₃/GdGaO dielectric stacks have been grown on GaAs for MOSFETs. This paper highlights variations in the characteristics of GdGaO as the Gd flux, Ga₂O flux and substrate temperature are changed. The growth rate, composition, crystallinity are discussed and the sheet resistance of final MOSFET structures are presented. The Gd compositional variation with depth is examined using Rutherford back scattering (RBS) and electron energy loss spectroscopy (EELS).     

Carrier transit delays in nanometer-scale GaAs MESFET's

MESFETs with gate lengths in the range of 40 to 300 nm with GaAs and AlGaAs buffer layers were characterized by high-frequency transit-time measurements. The total carrier transit time is interpreted as being composed of an intrinsic part, a drain delay, and a channel charging delay. The drain field's effect on the geometry of the gate depletion region, and the injection of carriers into the buffer layer are used to describe the origin of these delays and their limiting effect on the high-frequency performance of sub-0.1-μm gate-length MESFETs     

Parallel coupled-line bandpass filter with branch-line shape for g-band frequency

A parallel coupled-line planar bandpass filter (BPF) with branch-line shape using coplanar waveguide technology on GaAs substrate is presented. The unit parallel coupled-line BPF utilises a parallel coupled-line resonator with an open-ended stub which has suppression response of spurious band. Four unit parallel coupled-line BPFs are integrated with branch-line shape and open-circuit stubs on input and output ports are also integrated for improvement of rejection performance. The proposed fourth-order filter was fabricated on GaAs substrate with dielectric thickness of 50 m and gold thickness of 1.2 mum. The fabricated fourth-order BPF shows a 3 dB bandwidth from 177 to 209 GHz frequency range with insertion loss of 6.5 dB, rejection of 38 dB and return loss better than 12 dB. It has a high resolution fractional bandwidth of 17%.     

Effect of interface state trap density on the characteristics of n-type,enhancement-mode,implant-free In0.3Ga0.7As MOSFETs

The effect of interface state trap density, D_it, on the device characteristics of n-type, enhancement-mode, implant-free (IF) In_0.3Ga_0.7As MOSFETs [1], [2] has been investigated using a commercial drift-diffusion (DD) device simulation tool. Methodology has been developed to include arbitrary D_it distributions in the input simulation decks to more accurately fit the measured subthreshold characteristics of recently reported 1.0 μm gate length IF In_0.3Ga_0.7As MOSFETs [3]. The impact of interface states on a scaled 30 nm gate length IF MOSFET is also reported.     

Design and Characterisation of Titanium Nitride Subarrays of Kinetic Inductance Detectors for Passive Terahertz Imaging

We report on the investigation of titanium nitride (TiN) thin films deposited via atomic layer deposition (ALD) for microwave kinetic inductance detectors (MKID). Using our in-house ALD process, we have grown a sequence of TiN thin films (thickness 15, 30, 60 nm). The films have been characterised in terms of superconducting transition temperature \(T_\mathrm{c}\), sheet resistance \(R_\mathrm{s}\) and microstructure. We have fabricated test resonator structures and characterised them at a temperature of 300 mK. At 350 GHz, we report an optical noise equivalent power \(\hbox {NEP}_\mathrm{opt} \approx 2.3\times 10^{-15}~\hbox {W}/\sqrt{\hbox {Hz}}\), which is promising for passive terahertz imaging applications.     

Passive harmonic modelocking in monolithic compound-cavity laserdiodes

Passive harmonic modelocking operation of novel compound-cavity laser diodes is demonstrated. The modelocking rates can be readily scaled up into the terahertz domain and enable applications in terahertz imaging, medicine, ultrafast optical links, and atmospheric sensing     

50-nm T-gate metamorphic GaAs HEMTs with f/sub T/ of 440 GHz and noise figure of 0.7 dB at 26 GHz

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies.     

A Planar Gunn Diode Operating Above 100 GHz

We show the experimental realization of a 108-GHz planar Gunn diode structure fabricated in GaAs/AlGaAs. There is a considerable interest in such devices since they lend themselves to integration into millimeter-wave and terahertz integrated circuits. The material used was grown by molecular beam epitaxy, and devices were made using electron beam lithography. Since the frequency of oscillation is defined by the lithographically controlled anode-cathode distance, the technology shows great promise in fabricating single chip terahertz sources.