Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

In the present work, a high aspect ratio process (HARP) using a new O₃/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gapfill in sub-65-nm CMOS. Good gapfill performance up to aspect ratios greater than 10:1 was demonstrated. Since the HARP process does not attack the STI liner as compared to HDP, a variety of different STI liners can be implemented. By comparing HARP with HDP, the geometry dependence of nand p-FET performance due to STI stress is discussed     

Visualizing the doping profile of a silicon germanium HBT with polysilicon emitter using electron holography

Modern bipolar transistors use polysilicon emitters and an epitaxial grown silicon germanium (SiGe) base. For device optimization, both the SiGe base and the region of the diffused emitter is of special interest. In this paper, electron holography is applied to visualize and directly measure the two-dimensional distribution of the local potential in a high-performance SiGe heterojunction bipolar transistor. Special emphasis is put on investigating the region of the emitter diffused into the epitaxially grown base layer. In addition, we investigate the self-aligned base-link construction. We compare electron holographic measurements of the whole transistor to secondary ion mass spectrometric (SIMS) data and discuss the results.     

Influence of metal gate and capping film stress on TANOS cell performance

In this work it is shown that film stress in the gate stack of TANOS NAND memories plays an important role for cell device performance and reliability. Tensile stress induced by a TiN metal gate deteriorates TANOS cell retention compared to TaN gate material. However, the erase saturation level as well as cell endurance is improved by the use of a TiN gate. This trade-off between retention and erase saturation for TANOS cells is elaborated in detail.     

Highly Scalable Embedded Flash Memory With Deep Trench Isolation and Novel Buried Bitline Integration for the 90-nm Node and Beyond

In this paper, we embedded a Flash memory cell with 90-nm ground-rules in a high-performance CMOS logic process. A novel deep trench isolation (DTI) module enables an isolated p-well (IPW) bias scheme, leading to Flash with uniform channel program/erase by Fowler-Nordheim tunneling without gate induced drain leakage, a key feature for low-power portable electronics. The IPW concept leads to a compact cell design and a highly scalable high-voltage periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTI of each bitline (BL) from its neighboring BLs. We additionally present a buried BL (BBL) concept that links the source contacts of each individual BL via the IPW; thus, effectively eliminating one metal line per BL and reducing overall cell size. A conservative cell size shrink of about 40% can be achieved for a uniform channel program/erase-Flash cell with deep trench and BBL compared to a conventional 21F²cell.     

Generating geologically realistic 3D reservoir facies models using deep learning of sedimentary architecture with generative adversarial networks

This paper proposes a novel approach for generating 3-dimensional complex geological facies models based on deep generative models. It can reproduce a wide range of conceptual geological models while possessing the flexibility necessary to honor constraints such as well data. Compared with existing geostatistics-based modeling methods, our approach produces realistic subsurface facies architecture in 3D using a state-of-the-art deep learning method called generative adversarial networks (GANs). GANs couple a generator with a discriminator, and each uses a deep convolutional neural network. The networks are trained in an adversarial manner until the generator can create “fake” images that the discriminator cannot distinguish from “real” images. We extend the original GAN approach to 3D geological modeling at the reservoir scale. The GANs are trained using a library of 3D facies models. Once the GANs have been trained, they can generate a variety of geologically realistic facies models constrained by well data interpretations. This geomodelling approach using GANs has been tested on models of both complex fluvial depositional systems and carbonate reservoirs that exhibit progradational and aggradational trends. The results demonstrate that this deep learning-driven modeling approach can capture more realistic facies architectures and associations than existing geostatistical modeling methods, which often fail to reproduce heterogeneous nonstationary sedimentary facies with apparent depositional trend.     

Quarter micron BiCMOS technology platform with implanted-base- or SiGe-bipolar transistor for wireless communication ICs

We present a modular 0.25 μm ASIC-compatible, double-poly self-aligned BiCMOS technology comprising either an implanted-base 45 GHz bipolar transistor or a 80 GHz-HBT with selective SiGe-epitaxy. All passive devices for RF-design are integrated, including a 7 fF/μm² stacked MIS-/MIM-capacitor.     

Microstructured apertures in planar glass substrates for ion channel research

We have developed planar glass chip devices for patch clamp recording. Glass has several key advantages as a substrate for planar patch clamp devices. It is a good dielectric, is well-known to interact strongly with cell membranes and is also a relatively in-expensive material. In addition, it is optically neutral. However, microstructuring processes for glass are less well established than those for silicon-based substrates. We have used ion-track etching techniques to produce micron-sized apertures into borosilicate and quartz-glass coverslips. These apertures, which can be easily produced in arrays, have been used for high resolution recording of single ion channels as well as for whole-cell current recordings from mammalian cell lines. An additional attractive application that is greatly facilitated by the combination of planar geometry with the optical neutrality of the substrate is single-molecule fluorescence recording with simultaneous single-channel measurements.     

A framework for parallel computational physics algorithms on multi-core: SPH in parallel

In this paper, a simulation framework that enables distributed numerical computing in multi-core shared-memory environments is presented. Using multiple threads allows a single memory image to be shared concurrently across cores but potentially introduces race conditions. Race conditions can be avoided by ensuring each core operates on an isolated memory block. This is usually achieved by running a different operating system process on each core, such as multiple MPI processes. However, we show that in many computational physics problems, memory isolation can also be enforced within a single process by leveraging spatial sub-division of the physical domain. A new spatial sub-division algorithm is presented that ensures threads operate on different memory blocks, allowing for in-place updates of state, with no message passing or creation of local variables during time stepping. Additionally, the developed framework controls task distribution dynamically ensuring an events based load balance. Results from fluid mechanics analysis using Smoothed Particle Hydrodynamics (SPH) are presented demonstrating linear performance with number of cores.     

An events based algorithm for distributing concurrent tasks on multi-core architectures

In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application to a wide range of numerical simulation problems. Such problems involve time stepping or iteration algorithms where synchronization of multiple threads of execution is required. It is shown that traditional approaches to parallelism including message passing and scatter-gather can be improved upon in terms of speed-up and memory management. Using spatial decomposition to create orthogonal computational tasks, a new task management algorithm called H-Dispatch is developed. This algorithm makes efficient use of memory resources by limiting the need for garbage collection and takes optimal advantage of multiple cores by employing a “hungry” pull strategy. The technique is demonstrated on a simple finite difference solver and results are compared to traditional MPI and scatter-gather approaches. The H-Dispatch approach achieves near linear speed-up with results for efficiency of 85% on a 24-core machine. It is noted that the H-Dispatch algorithm is quite general and can be applied to a wide class of computational tasks on heterogeneous architectures involving multi-core and GPGPU hardware.