The process dependence on positive bias temperature aginginstability of p+(B) polysilicon-gate MOS devices

During positive bias temperature (BT) aging, a large number of interface traps on p⁺(B) polysilicon MOS devices are generated in the upper half of the bandgap without an increase in the charges trapped in the gate oxide. The increase in interface traps can be reduced by processes which exclude the hydrogen included during fabrication. The increase in the interface-state density is explained as follows. The generation of the interface traps is caused by hydrogen ions reaching at the SiO₂/Si interface through the gate oxide from the polysilicon-gate electrode. The hydrogen ions combine with activated boron and are released from the boron under positive BT aging. The increase in interface traps is formulated by equations which are derived from the above model     

A low-temperature MOS LSI process

A low-temperature process is proposed for the fabrication of MOS LSIs with very small dimensions. Since this process needs no thermal treatment after gate insulation, shallow source/drain junction, ultra-thin gate oxide, and Al gate electrode can be used. The key processes are self-aligned gate pattern reversion using Mo dummy gates and ECR SiO₂ lift-off, and planarized Al gate electrode filling using resist/Al etch-back. Test devices fabricated to demonstrate the feasibility of this process operate without trouble