Modeling subthreshold SOI logic for static timing analysis

A simple, yet realistic physics-based model is introduced to describe the subthreshold drain current of a MOSFET taking into account the body- and drain-voltage dependencies, including the short channel effects. This model, verified by SPICE simulations, describes adequately the pseudotriode and pseudosaturation regions of MOS transistors operated below V/sub T/. It can be applied for predicting bulk- or partially depleted (PD) SOI CMOS circuit operation. Analytical expressions derived for the logic switching threshold and delay are applied to predict the performance of CMOS-SOI inverters.     

Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability

Power switch transistors are very effective in cutting the leakage currents of digital circuits in a deep-freeze mode, by de-supplying unused blocks. Among existing power switch transistors, Super Cut-off CMOS (SCCMOS) is the most suited to a low supply voltage environment since it uses a low threshold voltage transistor. This power switch type achieves good leakage reduction results, provided that an optimal voltage is applied on its gate in order to maximize the leakage gain. This optimal voltage value, depending on the operating conditions (process, voltage, temperature), cannot be determined at the design level. A polarization circuit, that automatically finds the optimal bias voltage whatever the environment conditions, was therefore designed and fabricated. This circuit, made in Bulk 65 nm technology, achieves more than two decades leakage current reduction at the power switch level, for a power dissipation overhead of 45 nW at ambient temperature. A very simple scheme is also presented to alleviate the voltage stress applied on the dielectric in case of an ageing of the latter, increasing its time-to-breakdown by several orders of magnitude.