Architecture, design, and modeling of the OPSnet asynchronous optical packet switching node

An all-optical packet-switched network supporting multiple services represents a long-term goal for network operators and service providers alike. The EPSRC-funded OPSnet project partnership addresses this issue from device through to network architecture perspectives with the key objective of the design, development, and demonstration of a fully operational asynchronous optical packet switch (OPS) suitable for 100 Gb/s dense-wavelength-division multiplexing (DWDM) operation. The OPS is built around a novel buffer and control architecture that has been shown to be highly flexible and to offer the promise of fair and consistent packet delivery at high load conditions with full support for quality of service (QoS) based on differentiated services over generalized multiprotocol label switching.     

Communication modeling of multicast in all-port wormhole-routed NoCs

Multicast is one of the most frequently used collective communication operations in multi-core SoC platforms. Bus as the traditional interconnect architecture for SoC development has been highly efficient in delivering multicast messages. Since the bus is non-scalable, it can not address the bandwidth requirements of the large SoCs. The networks on-chip (NoCs) emerged as a scalable alternative to address the increasing communication demands of such systems. However, due to its hop-to-hop communication, the NoCs may not be able to deliver multicast operations as efficiently as buses do. Adopting multi-port routers has been an approach to improve the performance of the multicast operations in interconnection networks. This paper presents a novel analytical model to compute communication latency of the multicast operation in wormhole-routed interconnection networks employing asynchronous multi-port routers scheme. The model is applied to the Quarc NoC and its validity is verified by comparing the model predictions against the results obtained from a discrete-event simulator developed using OMNET++.     

III–V semiconductor waveguiding devices using adiabatic tapers

In the past few years much effort has been put into the fabrication and optimization of III–V semiconductor waveguiding devices with integrated adiabatic mode size converters (tapers). By integrating a taper with a waveguide device, one wants to reduce the coupling losses and the packaging cost of OEICs in future optical communication systems. This paper gives an overview of different taper designs, their performance and the technological approaches used in realizing such tapered devices.     

An analytical model of broadcast in QoS-aware wormhole-routed NoCs

Networks-on-Chip (NoC) emerged to address the technological and design issues related to development of large systems-on-chip (SoCs). Due to diversity of the application's performance requirements, most NoC architectures offer supports for quality of service (QoS). Also, to utilize the available bandwidth efficiently, they might implement mechanisms for delivering collective communication operations. This paper presents an analytical model to predict the average latency of wormhole-routed prioritized broadcast communication in NoCs. The model assumes that the network uses all-port routers scheme and offers differentiated services-based QoS. To verify the analysis, the model predictions are compared against the results obtained from a discrete-event simulator developed using OMNET++.     

An analytical performance model for the Spidergon NoC with virtual channels

The Spidergon Network-on-Chip (NoC) was proposed to address the demand for a fixed and optimized communication infrastructure for cost-effective multi-processor Systems-on-Chip (MPSoC) development. To deal with the increasing diversity in quality of service requirements of SoC applications, the performance of this architecture needs to be improved. Virtual channels have traditionally been employed to enhance the performance of the interconnect networks. In this paper, we present analytical models to evaluate the message latency and network throughput in the Spidergon NoC and investigate the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions. Moreover an FPGA implementation of the Spidergon has been developed to provide an accurate analysis of the cost of employing virtual channels in this architecture.     

A compact test structure for characterisation of leakage currents in sub-micron CMOS technologies

This paper presents a compact test structure for the characterisation and modelling of leakage currents in sub-micron CMOS technologies, with which all leakage components can be directly extracted automatically and input/output influence is cancelled. The test structure can also be used for measurement of intrinsic I_ddq for defect detection.     

Monolithic integration of a spot size transformer with a planarburied heterostructure InGaAsP/InP-laser using the shadow masked growthtechnique

We present a vertically tapered InGaAsP/InP planar buried heterostructure (PBB) laser for low loss coupling to single-mode fibers. To achieve the vertical tapering we make use of the shadow masked growth technique. Tapered lasers with beam divergences of 15° in both lateral and transverse directions were realized. In comparison with untapered lasers, the coupling losses to cleaved single-mode fibers could be reduced by 4.8 dB down to 5.8 dB