Quantum Transport Simulation of Experimentally Fabricated Nano-FinFET

We have utilized the contact-block-reduction (CBR) method, which we extended to allow a charge self-consistent scheme, to simulate experimentally fabricated 10-nm-FinFET device. The self-consistent CBR simulator has been modified to simulate devices with channels along arbitrary crystallographic orientation. A series of fully quantum-mechanical transport simulations has been performed. First, the fin extension length and doping profile have been calibrated to match the experimental data. The process control window for the threshold voltage as a function of fin extension has been extracted for the considered device. Then, a set of transfer characteristics and gate leakage currents have been calculated for different drain voltages. The simulation results have been found to be in good agreement with the experimental data in the subthreshold regime. The device turn-off and turn-on behavior has been examined for different fin widths: 12 (experimental), 10, 8, and 6 nm. Finally, the subthreshold slope degradation at high temperatures has been studied     

Modeling thermal effects in nano-devices

For the purpose of investigating the role of self-heating effects on the electrical characteristics of nano-scale devices, we implemented a two-dimensional Monte Carlo device simulator that self-consistently includes the solution of the energy balance equations for both, acoustic and optical phonons. We find less degradation in the current in smaller device structures because of the more pronounced velocity overshoot.     

Scaled silicon MOSFETs: degradation of the total gate capacitance

We use a fully quantum-mechanical model to study the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs. We show that, when the device is in weak and moderate inversion, the inclusion of image and many-body exchange-correlation effects increases both the inversion layer and total gate capacitances and shifts the N_s=N_s(VG) characteristics of the device toward lower gate voltages     

Study of self-heating effects in SOI and conventional MOSFETs with electro-thermal particle-based device simulator

In this paper we present a study of self-heating effects in nanoscale SOI (Silicon-On-Insulator) devices and conventional MOSFETs using an in-house electro-thermal particle-based device simulator. We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional (2D) and the three-dimensional version (3D) of the tool) and then we present a series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in SOI technology. Our simulation results for planar SOI devices (using 2D version of the tool) show that in the smallest devices considered, heat dissipation occurs in the contacts, not in the active channel region of the device. This is because of two factors: pronounced velocity overshoot effect and the smaller thermal resistance of the buried oxide layer. We propose methods in which heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. To simulate self heating in nanowire transistors, the 2D simulator was extended to three spatial dimensions. We study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel in nanowire transistors, the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel. Finally, we examine the importance of self-heating effects in conventional MOSFETs used for low-power applications. We find that the average temperature increase obtained with our simulator of about 10 K is almost identical to the value that has to be used in low-power circuit simulations.     

Scaled silicon MOSFET's: universal mobility behavior

We use a fully quantum-mechanical model to study the inversion layer mobility in a silicon MOS structure. The importance of depletion charge and surface-roughness scattering on the effective electron mobility is examined. The magnitude of the mobility is found to be considerably reduced by both depletion charge and interface-roughness scattering. The appropriate weighting coefficients a and b for the inversion and depletion charge densities in the definition of the effective electric field, which eliminate the doping dependence of the effective electron mobility, are also calculated. These are found to differ from the commonly used values of 0.5 and 1. In addition, the weighting coefficient for the depletion charge density is found to be significantly influenced by the actual shape of the doping profile and can be either >1 or <1     

Band-Structure and Quantum Effects on Hole Transport in p-MOSFETs

Using a Monte Carlo method, we investigate hole transport in ultrasmall p-channel Si MOSFETs with gate lengths of 25 nm. The device simulator couples a 2D Poisson solver with a discretized 6 × 6 k.p Hamiltonian solver that includes the effect of the confining potential and provides the subband structure in the channel region. In addition, carriers in the source and drain regions are treated as quasi 3D particles and the band-structure information is included by solving for the eigenenergies of a more compact 6× 6 k.p Hamiltonian.     

Is self-heating responsible for the current collapse in GaN HEMTs?

AlGaN/GaN high-electron mobility transistors (HEMTs) are a very promising technology for switching and radio frequency power applications due to the high saturation velocity and large breakdown field of the GaN material. However, the electrical reliability of this material system in both the on and the off-state operation regimes is still a fundamental problem to be solved before the widespread use of this technology can be made.     

Current progress in modeling self-heating effects in FD SOI devices and nanowire transistors

In this paper we summarize 6 years of work on modeling self-heating effects in nano-scale devices at Arizona State University (ASU). We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional and the three-dimensional version of the tool) and then we present series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in silicon on insulator technology (SOI). Our simulation results also show that in the smallest devices considered the heat is in the contacts, not in the active channel region of the device. Therefore, integrated circuits get hotter due to larger density of devices but the device performance is only slightly degraded at the smallest device size. This is because of two factors: pronounced velocity overshoot effect and smaller thermal resistance of the buried oxide layer. Efficient removal of heat from the metal contacts is still an unsolved problem and can lead to a variety of non-desirable effects, including electromigration. We propose ways how heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. We also study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel and the self-heating effects. We illustrate the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel.