Elliptic curve cryptography on embedded multicore systems

The increasing use of network-connected embedded devices and online transactions creates a growing demand of network security for embedded systems. The security requirements, such as authentication, confidentiality and integrity, always make computationally intensive processes and can easily become the bottleneck of the related applications. In this paper we implement Elliptic Curve Cryptography (ECC) (Miller in Lecture Notes in Computer Science, vol. 218, pp. 417–426, 1985; Koblitz in Math. Comput. 48:203–209, 1987) on an embedded multicore system, and explore the task scheduling methods in different levels. First, we propose an instruction scheduling method that utilizes all the cores to perform one modular operation in parallel. Second, we perform multiple modular operations with multiple cores in parallel. The performance of those two implementations is compared and a scheduling method combining these two types of parallelism is proposed. We discuss the details of our proposed method by using an FPGA implementation of ECC over a prime field.     

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

Substrate noise is a major obstacle for mixed-signal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the Vdd-Vss admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. In this paper, we address: 1) the dependence of the Vdd-Vss admittance on the different states of the circuit, the supply voltage, and the interconnect, and 2) the computation of the total supply current with ground bounce. By using a fast and accurate macromodeling approach, the Vdd-Vss admittances of several test circuits are computed with 2%-3% error relative to the values simulated from the complete SPICE level netlist, but several orders of magnitude faster in CPU time and with 10% maximum error relative to the measurements on a test ASIC fabricated in a 0.18-/spl mu/m CMOS process on a high-ohmic substrate with 18 /spl Omega//spl middot/cm resistivity. The measurements also show that this admittance mainly depends only on the connectivity of the gates to the supply rail rather than their connectivity among each other.     

A Low Power DSP Engine for Wireless Communications

This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wireless digital systems and speech applications. Besides providing a basic instruction set, similar to current day 16-bit DSP's, it contains distinctive architectural features and unique instructions, which make the engine highly efficient for compute-intensive tasks such as vector quantization and Viterbi operations. The datapath contains two Multiply-Accumulate units and one ALU. The external memory bandwidth is kept to two data busses and two corresponding address busses. Still, the internal bus network is designed such that all three units are operating in parallel. This parallelism is reflected in the performance benchmarks. For example, an FIR filter of N taps will take N/2 instruction cycles compared to N for a general purpose 16-bit DSP, and it will require only half the number of memory accesses of a general purpose DSP. This efficiency is reflected in the very low MIPS requirement to implement cellular standards.     

A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

This paper describes a low-power synchronous pulsed signaling scheme on a fully AC coupled multidrop bus for board-level chip-to-chip communications. The proposed differential pulsed signaling transceiver achieves a data rate of 1 Gb/s/pair over a 10-cm FR4 printed circuit board, which dissipates only 2.9 mW (2.9 pJ/bit) for the driver and channel termination and 2.7 mW for the receiver pre-amplifier at 500 MHz. The fully AC coupled multipoint bus topology with high signal integrity is proposed that minimizes the effect of inter-symbol interference (ISI) and achieves a 3 dB corner frequency of 3.2 GHz for an 8-drop PCB trace. The prototype transceiver chip is implemented in a 0.10-/spl mu/m 1.8-V CMOS DRAM technology and packaged in a WBGA. It occupies an active area of 330/spl times/85 /spl mu/m/sup 2/.     

Microscopic investigation of the formation of a thermoset wheat gluten network in a model system relevant for bread making

Although the impact of heat on molecular properties of wheat gluten is well understood, changes in its microstructure have rarely been studied. Here, formation of the thermoset gluten network in a model system relevant for bread baking was studied with confocal laser scanning microscopy and protein network analysis. From 65 °C onwards, gluten converts from thick aligned protein strands in a highly branched and homogeneous network of small thin protein threads. Neither gliadin incorporation in the network nor application of aqualysin 1, the thermo-active serine peptidase from Thermus aquaticus which recently has been reported to hydrolyse gluten proteins in dough only at temperatures exceeding 80 °C, impacts on the gluten microstructure. As starch causes structure setting itself and thereby decreases protein mobility, molecular scale changes in the gluten network at temperatures exceeding 80 °C brought about by aqualysin 1 do not impact its microstructure.     

A Practical Attack on KeeLoq

KeeLoq is a lightweight block cipher with a 32-bit block size and a 64-bit key. Despite its short key size, it is used in remote keyless entry systems and other wireless authentication applications. For example, there are indications that authentication protocols based on KeeLoq are used, or were used by various car manufacturers in anti-theft mechanisms. This paper presents a practical key recovery attack against KeeLoq that requires 2¹⁶ known plaintexts and has a time complexity of 2^44.5 KeeLoq encryptions. It is based on the principle of slide attacks and a novel approach to meet-in-the-middle attacks.     

Efficient and secure hardware

Smart city or smart grid, e-Health, e-ID, e-government, e-mobility and many more e-trends are societal moves coming to us. None of them will however become a reality without secure, efficient, embedded implementations of cryptographic algorithms into the electronic devices that support these society changers.     

Domain-specific codesign for embedded security

Systems with multiple design domains require codesign of application domains. Dedicated hardware processors implement the application domains and software integrates them. The authors use ThumbPod, a prototype embedded security application, for remote identification applications such as intelligent keys or electronic payments. The device combines security, biometrics, and networking domains. Additional software support consists of a dynamic application download using the Java application manager. Sun's K virtual machine offers an infrastructure for secure code download and execution. The virtual machine also integrates the cryptoprocessor through a native interface.