Experimental and numerical assessment of gate-lag phenomena in AlGaAs-GaAs heterostructure field-effect transistors (FETs)

Gate-lag effects are characterized in AlGaAs-GaAs heterostructure field-effect transistors (HFETs) by means of measurements and numerical device simulations. Gate lag increasingly affects device switching at increasing ungated recess extension, suggesting that responsible deep levels be located at the ungated, recess surface of the HFET. Gate lag diminishes by making the off-state gate-source voltage less negative and by increasing the drain bias. Increasing the temperature makes the turn-on transient faster at low drain bias, while slightly delaying it at high drain bias. Numerical device simulations accounting for acceptor-like traps at the ungated surface predict gate-lag phenomena in good agreement with experiments, reproducing correctly the observed bias and temperature dependences. Simulations show that surface states behave, during the turn-on transient, as hole traps capturing holes attracted at the ungated surface by the negative trapped charge.     

Influence of impact-ionization-induced base current reversal onbipolar transistor parameters

In this paper we describe a set of measurements representing a complete characterization of impact-ionization effects in bipolar transistors. We demonstrate that impact-ionization significantly influences the dependence of base resistance on current and voltages applied to the device. A dc method for the simultaneous extraction of all parasitic resistances in bipolar transistors is presented. The method can separate the influence of current-crowding on the base resistance from that of base width and conductivity modulation; the collector parasitic resistance is measured in the active region. Starting from the parameters extracted by means of these techniques, a complete and accurate circuit-model of impact-ionization effects can be defined     

Gate oxide reliability improvement related to dry local oxidation of silicon

Gate oxide reliability can be effectively improved by using dry field oxidation instead of the conventional wet one. The obtained improvement is suggested to occur because of a better oxide quality in the active region border due to the absence of the characteristic defects induced by wet local oxidation.     

Characterization and analysis of trap-related effects in AlGaN–GaN HEMTs

Traps are characterized in AlGaN–GaN HEMTs by means of DLTS techniques and the associated charge/discharge behavior is interpreted with the aid of numerical device simulations. Under specific bias conditions, buffer traps can produce “false” surface-trap signals, i.e. the same type of current-mode DLTS (I-DLTS) or ICTS signals that are generally attributed to surface traps. Clarifying this aspect is important for both reliability testing and device optimization, as it can lead to erroneous identification of the degradation mechanism, thus resulting in wrong correction actions on the technological process.     

Prediction of impact-ionization-induced snap-back in advanced Sin-p-n BJT's by means of a nonlocal analytical model for the avalanchemultiplication factor

The authors point out that when a triangular shape for the electric field in the base-collector space-charge region of an n-p-n Si BJT (bipolar junction transistor) is assumed, the electron mean energy can be calculated analytically from a simplified energy-balance equation. On this basis a nonlocal-impact-ionization model, suitable for computer-aided circuit simulation, has been obtained and used to calculate the output characteristics at constant emitter-base voltage (grounded base) of advanced devices. Provided the experimental bias-dependent value of the base parasitic resistance is accounted for in the device model, the base-collector voltage at which impact-ionization-induced snap-back occurs can be accurately predicted     

Investigation of High-Electric-Field Degradation Effects in AlGaN/GaN HEMTs

High-electric-field degradation phenomena are investigated in GaN-capped AlGaN/GaN HEMTs by comparing experimental data with numerical device simulations. Under power- and OFF-state conditions, 150-h DC stresses were carried out. Degradation effects characterizing both stress experiments were as follows: a drop in the dc drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the aforementioned degradation modes. Experiments also showed that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the OFF-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under the power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge toward the drain contact, whereas, under the OFF-state stress, trap generation is supposed to take place in a narrower portion of the drain-access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters.     

Reliability of GaN High-Electron-Mobility Transistors: State of the Art and Perspectives

Failure modes and mechanisms of AlGaN/GaN high-electron-mobility transistors are reviewed. Data from three de-accelerated tests are presented, which demonstrate a close correlation between failure modes and bias point. Maximum degradation was found in "semi-on" conditions, close to the maximum of hot-electron generation which was detected with the aid of electroluminescence (EL) measurements. This suggests a contribution of hot-electron effects to device degradation, at least at moderate drain bias (V_DS<30 V). A procedure for the characterization of hot carrier phenomena based on EL microscopy and spectroscopy is described. At high drain bias (V_DS>30-50 V), new failure mechanisms are triggered, which induce an increase of gate leakage current. The latter is possibly related with the inverse piezoelectric effect leading to defect generation due to strain relaxation, and/or to localized permanent breakdown of the AlGaN barrier layer. Results are compared with literature data throughout the text.     

DC-to-RF dispersion effects in GaAs- and GaN-based heterostructure FETs: performance and reliability issues

The performance and reliability implications of DC-to-RF dispersion effects are addressed. The proposed physical explanations and technological counteractions are reviewed. GaAs- and GaN-based FET technologies are considered, trying to point out both similar and peculiar aspects.     

Analysis of current collapse effect in AlGaN/GaN HEMT: Experiments and numerical simulations

In this work, current collapse effects in AlGaN/GaN HEMTs are investigated by means of measurements and two-dimensional physical simulations. According to pulsed measurements, the used devices exhibit a significant gate-lag and a less pronounced drain-lag ascribed to the presence of surface/barrier and buffer traps, respectively. As a matter of fact, two trap levels (0.45 eV and 0.78 eV) were extracted by trapping analysis based on isothermal current transient. On the other hand, 2D physical simulations suggest that the kink effect can be explained by electron trapping into barrier traps and a consequent electron emission after a certain electric-field is reached.