ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

Indoor body-area channel model for narrowband communications

Using wireless sensors placed on a person to continuously monitor health information is a promising new application. At the same time, new low-power wireless standards such as Bluetooth and Zigbee have been proposed for short range, low data-rate communication matching the requirements of these bio-medical applications. However, there are currently few measurements or models describing propagation around the body. To address this problem, electromagnetic waves near the torso are measured and a statistical model is derived for communication in the 915 MHz and 2.45 GHz industrial, scientific and medical bands associated with Zigbee and Bluetooth. Measurement setup and statistical analysis are described.     

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.     

Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates

In mixed analog-digital designs, digital switching noise is an important limitation for the performance of analog and RF circuits. This paper reports a physical model describing the impact of digital switching noise on LC-tank voltage-controlled oscillators (VCOs) in lightly doped substrates. The model takes into account the propagation from the source of substrate noise to the different components in the VCO and the resulting modulation of the oscillator frequency. The model is validated with measurements on a 3.5-GHz LC-tank VCO designed in 0.18-/spl mu/m CMOS. It reveals that for this VCO, impact occurs mainly via the nonideal metal ground lines for lower frequencies and low tuning voltage and via the integrated inductors for higher frequencies and high tuning voltage. To make the design immune to substrate noise, the parasitic resistance of the on-chip ground interconnect has to be kept as low as possible and inductors have to be shielded. Hence, the developed model allows investigating the dominant mechanisms behind the impact of substrate noise on a VCO, which is crucial information for achieving a substrate noise immune design.     

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

Substrate noise is a major obstacle for mixed-signal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the Vdd-Vss admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. In this paper, we address: 1) the dependence of the Vdd-Vss admittance on the different states of the circuit, the supply voltage, and the interconnect, and 2) the computation of the total supply current with ground bounce. By using a fast and accurate macromodeling approach, the Vdd-Vss admittances of several test circuits are computed with 2%-3% error relative to the values simulated from the complete SPICE level netlist, but several orders of magnitude faster in CPU time and with 10% maximum error relative to the measurements on a test ASIC fabricated in a 0.18-/spl mu/m CMOS process on a high-ohmic substrate with 18 /spl Omega//spl middot/cm resistivity. The measurements also show that this admittance mainly depends only on the connectivity of the gates to the supply rail rather than their connectivity among each other.     

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation

The successful realization of a wireless body area network (WBAN) requires innovative solutions to meet the energy consumption budget of the autonomous sensor nodes. The radio interface is a major challenge, since its power consumption must be reduced below 100 /spl mu/W (energy scavenging limit). The emerging ultra-wide-band (UWB) technology shows strong advantages in reaching this target. First, most of the complexity of an UWB system is in the receiver, which is a perfect scenario in the WBAN context. Second, the very little hardware complexity of a UWB transmitter offers the potential for low-cost and highly integrated solutions. Finally, in a pulse-based UWB scheme, the transmitter can be duty-cycled at the pulse rate, thereby reducing the baseline power consumption. We present a low-power UWB transmitter that can be fully integrated in standard CMOS technology. Measured performances of a fully integrated pulse generator are provided, showing the potential of UWB for low power and low cost implementations. Finally, using a WBAN channel model, we present a comparison between our UWB solution and state-of-the-art low-power narrow-band implementations. This paper shows that UWB performs better in the short range due to a reduced baseline power consumption.     

The Influence of Inverter Feeding on the Apparent Stray Inductance of Asynchronous Machines

The stray inductance is an important parameter for the design of inverters feeding asynchronous machines. Measurements are proposed which are relevant for determining the apparent stray inductance of an inverter-fed asynchronous machine. These measurements show that the apparent stray inductance is considerably smaller than the one obtained with classical sinusoidal methods. This amounts to smaller commutating capacitors in current source inverter (CSI) motor drives. A theoretical explanation for this phenomenon is presented and confirmed by calculation.     

Efficient symbolic computation of approximated small-signalcharacteristics of analog integrated circuits

A symbolic analysis tool is presented that generates simplified symbolic expressions for the small-signal characteristics of large analog integrated circuits. The expressions are approximated while they are computed, so that only those terms are generated which remain in the final expression. This principle causes drastic savings in CPU time and memory, compared with previous symbolic analysis tools. In this way, the maximum size of circuits that can be analyzed, is largely increased. By taking into account a range for the value of a circuit parameter rather than one single number, the generated expressions are also more generally valid. Mismatch handling is explicitly taken into account in the algorithm. The capabilities of the new tool are illustrated with several experimental results     

Occurrence,prevention and remediation of toxigenic fungi and mycotoxins in silage: a review

Ruminants are considered to be less sensitive towards mycotoxins than monogastric animals because rumen microbiota have mycotoxin‐detoxifying capacities. Therefore the effect of mycotoxins towards ruminants has been studied to a lesser extent compared with monogastric animals. Worldwide, a high proportion of the ruminant diet consists of silages made of forage crops (i.e. all parts of the crop above the stubble are harvested). In practice, silages are often contaminated with multiple mycotoxins. Exposure to a cocktail of mycotoxins can hamper animal production and have severe health consequences. In this article the different aspects associated with mycotoxin contamination of silage are reviewed ‘from seed to feed’. An overview is given on the occurrence of toxigenic fungal species and their concomitant mycotoxins in forage crops before and after ensiling. The mycotoxin load of visually non‐mouldy samples and mouldy hot spots within the same silo is also compared. Subsequently, this review delves into different problem‐solving strategies. A logical first step is prevention of mould growth and mycotoxin production in the field, during harvest and during ensiling. If prevention should fail, several remediation strategies are available. These are listed, mainly focusing on the possibilities of microbial degradation of mycotoxins in vivo in silage. © 2015 Society of Chemical Industry     

Algorithm for efficient symbolic analysis of large analoguecircuits

An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large analogue circuits. The expressions are approximated while they are computed, so that only the most significant terms are generated which remain in the final expression. This principle leads to dramatic savings in CPU time and memory compared to existing techniques, significantly increasing the maximum size of circuits that can be analysed. By taking into account a range for the value of a circuit parameter rather than one single number the generated symbolic expressions are also generally valid