The impact of metal-1 plasma processing-induced hot carrierinjection on the characteristics and reliability of n-MOSFETs

We report on plasma processing-induced damage to sub-half-micron n-MOSFETs that is invoked by potential differences between device terminals during metal-1 plasma processing. The damage mechanism is identified as hot carrier (HC) injection promoted by the layout of metal-1 interconnect. Using conventional and modified charge pumping techniques as well as transistor parameter measurements, we also investigate the impact of the damage on device reliability by applying Fowler-Nordheim (FN) and hot carrier stresses. The results show the severe impact of this damage on device reliability, which is attributed to trapping of positive charge at the drain edge that is enough to shorten the device channel     

Microwave performance of a digital alloy barrierAl(Sb,As)/AlSb/InAs heterostructure field-effect transistor

High-speed, digital alloy barrier-based, Al(Sb,As)/AlSb/InAs heterostructure field-effect transistors (HFETs) fabricated using a standard mesa process are demonstrated. Current gain cutoff frequencies f_T of 38.5 GHz were extracted from the measured scattering parameters for devices with a 0.6-μm gate length and a 3-μm source-to-drain separation. A significant output conductance depressed f_max to 40 GHz. The results show the feasibility and potential of InAs/AlSb-based HFETs for high-speed electronics applications     

A comparison between plasma charging-damage and inductive-damage: Damage response to Fowler-Nordheim stress

This paper reports on the results of a study performed to compare the effects of charging damage and inductive damage to 0.5 μm n-channel MOSFETs arising from plasma etching at the gate-definition etch and metal-1 etch levels, respectively. The MOSFETs were fabricated on 200 mm p/p+ silicon wafers using a full CMOS process. The gate-definition etch step was performed using a chlorine-based chemistry and the metal etch step was done using a BCl₃/N₂/Cl₂ plasma. It is found that charging damage is electrically inactive after the full CMOS process flow; however, it is electrically activated by Fowler-Nordheim (F-N) stress when charging damage is clearly seen to correlate with the area of charging antenna in the device. Inductive damage, on the other hand, is seen to impact transistor parameters directly after the CMOS process and before the application of F-N stress. This is attributed to distinctly different mechanisms that are responsible for the creation of the two types of damage: charging damage arises from a dc current stress, whereas inductive damage is suggested to arise from ac current stress.     

High-transconductance InAs/AlSb heterojunction field-effecttransistors with δ-doped AlSb upper barriers

The authors report the fabrication and temperature-dependent characterization of InAs/AlSb quantum-well heterojunction field-effect transistors (HFETs). Devices with electron sheet concentrations of 3.8×10¹² cm^-2 and low-field electron mobilities of 21000 cm²/V-s have been realized through the use of Te δ-doping sheets in the upper AlSb barrier. One device with a 2.0-μm gate length showed a peak extrinsic transconductance of 473 mS/mm at room temperature. Gate leakage current, operating current density, and extrinsic transconductance were found to decrease with decreasing temperature     

Charge injection using gate-induced-drain-leakage current forcharacterization of plasma edge damage in CMOS devices

In this paper, we describe the application of gate-induced-drain-leakage (GIDL) current for the characterization of gate edge damage which occurs during the plasma etch processes. We show from experimental and simulation results that when the channel is biased in accumulation and with the drain-substrate junction reverse biased, charge injection is localized in the gate-drain overlap region. Under this localized charge injection (LCI) mode of operation, the gate voltage is a function of edge oxide thickness which in turn can be related to the plasma damage received during the poly-etch and subsequent spacer oxide formation. The detailed mechanism of localized charge injection for a study of plasma edge damage is explained along with the experimental demonstration of this technique using submicron MOSFET's     

Sinusoidal AC stressing of thin-gate oxides and oxide/siliconinterfaces in 0.5-μm n-MOSFETs

Sinusoidal ac signals are applied to 90-Å thick gate-oxide in 0.5-μm n-MOSFETs. The objective is to emulate ac stressing to devices, recently reported to occur during plasma processes. AC stressing is found to be more damaging to the oxide and oxide/silicon interface when compared to dc stressing. The damage induced by the ac stress is observed to depend on the signals frequency and amplitude. It is proposed that carrier hopping is primarily responsible for oxide current and device damage observed following the ac stress. This hopping current is insignificant during high-field dc stress when Fowler-Nordheim tunneling becomes the dominant conduction mechanism     

Cyclic current-voltage characterization applied to edge damageevaluation in gate definition plasma etching

A simple two-terminal cyclic current-voltage (I-V) measuring approach is used to monitor damage in gate definition plasma etching of poly-Si gate 70 Å oxide MOS structures. This new technique is used to identify the presence of trapping and near-surface silicon substrate generation lifetime changes due to edge exposure