Comparison of ATM switching architectures

Clear examination of work currently done within CCITT indicates the importance of a broadband telecommunication network. As this network should be capable of integrating all services in an efficient way—in order to reduce cost—the asynchronous transfer mode (ATM) was selected by CCITT as the target transfer mode for implementing the broadband integrated services digital network (BISDN). This selection implies that the switching nodes in the BISDN network are capable of supporting this high-speed packet and connection-orientated technique. Within the literature different switching node architectures based upon ATM have been proposed. All of these architectures should meet the high-speed and high-throughput requirements so as to cope with the delay and jitter performance objectives. In a first step this paper describes alternative switching techniques for the basic building block (switching element) of a switching node. A common model architecture of the switching element is drafted. A classification of switching elements described in the literature is derived and the influence on the complexity and performance is weighted. In a second step the switching node architecture is further elaborated according to the control and flexibility requirements. Core (switching) and edge (switching related) functions are listed, and possible functional partitionings are discussed. Finally, these ATM switching architectures are compared according to a background frame consisting of several straightforward comparison points such as the buffering strategy, the internal routeing method, the switching overhead, the connection-orientated or connectionless operation, etc.     

Detector-noise suppression by appropriate CR-(RC)nshaping

The influence of the order n of a semi-Gaussian CR-(RC)ⁿ shaper on the signal-to-noise ratio of a read-out system, subject to detector 1/f and 1/f² noise, is presented by the author. Normalised equivalent noise charges, ENC(n), as a function of n for the 1/f and 1/f² noise, respectively, are calculated and presented. An alternative solution to circumvent the problem of the singularity in the Beta function is discussed, which is related to the 1/f noise. Conclusions and some guidelines are derived from the obtained data     

A low-power high-gain transresistance BiCMOS pulse amplifier forcapacitive detector readout

A low-power, high-gain amplifier for detector readout is discussed. The amplifier is balanced, fully differential in circuit topology, and symmetrical in layout, making it radiation tolerant and relatively insensitive to varying magnetic fields in the large detector. Before irradiation, the circuit has a measured differential gain of 110 mV/4 fC, an average 10/90% rise time t_10/90% of 19 ns, a noise figure of 433⊕93·(C_t)^1.08 electrons, e^-, and a power consumption of 750 μW. To keep the core amplifier stable, a low-power super-low gain-bandwidth (SL-GBW) amplifier with a small area is used and also discussed. The SL-GBW amplified has a transition frequency f_T of 38 kHz (including the gain stage, A), a power consumption of 150 nW, a phase margin (PM) of ≈70°, an area of 300×36 μm², and a minimum current per transistor of 7 nA, which is far above the leakage current after irradiation. The complete circuit was implemented in the radiation hard SOI-SIMOX BiCMOS-PJFET technology of DMILL     

A BiCMOS front-end system with binary delay line for capacitivedetector read-out

As part of the entire readout chip, a low-power high-gain transresistance amplifier has been developed, followed by a high-speed, low-power small offset comparator and a binary delay line. The amplifier is balanced, fully differential in circuit topology, and symmetrical in layout, making it radiation tolerant and relatively insensitive to varying magnetic fields. Also, the comparator is fully symmetrical with a balanced input stage. Before irradiation (pre-rad) the transresistance amplifier has a measured differential gain of 110 mV/4 fC, an average 10/90% rise time (t_10/90%) of 20 to 50 ns depending on the bias conditions, a noise figure of 433⊕93.(C_t)^1.08 (where the symbol ⊕ stands for √(()²+() ²)) electrons (e^-), and a power consumption of 750 μW. The comparator uses bipolar transistors in the regenerative stage resulting in a small offset, a sensitivity <1.5 mV, and a power consumption of ≈350 μW at 40 MHz. The maximum pre-rad frequency at which the comparator is still functioning correctly is ≈100 MHz. Pre-rad, the binary delay line has a delay of 2.1 μs at 40 MHz and a power consumption of ≈450 μW/channel for a four-channel design. The complete readout channel-amplifier, comparator, and binary delay line-consumes ≈1.5 mW. The entire readout system was implemented in the radiation-hard 0.8-μm SOI-SIMOX BiCMOS-PJFET technology of DMILL     

Current mode charge pulse amplifier in CMOS technology for use withparticle detectors

0This amplifier is intended to be part of the front-end of a larger read-out chip to be used with particle detectors. The demands of read-out electronics are low power, low noise and high speed. At the input a charge pulse of 25000 electrons (4fC) is applied to study the behaviour of the amplifier. The amplifier has a gain of ±12 mV/fC depending on the biasing condition, a peaking time of 35 ns and a power consumption of <500 μW     

Appropriate (CR)m-(RC)n shaping for fastbipolar front-end read-out

The author presents a study of the influence of the order, n and m, of a (CR)^m-(RC)ⁿ shaper on the signal-to-noise, S/N, ratio of a read-out system, subject to input referred f² noise emitted by the bipolar input transistor. As a function of n and m, normalised equivalent noise charges, ENC(n, n), are calculated. Conclusions and some guidelines for filter design are derived from the data obtained