An immuno-wall microdevice exhibits rapid and sensitive detection of IDH1-R132H mutation specific to grade II and III gliomas

World Health Organization grade II and III gliomas most frequently occur in the central nervous system (CNS) in adults. Gliomas are not circumscribed; tumor edges are irregular and consist of tumor cells, normal brain tissue, and hyperplastic reactive glial cells. Therefore, the tumors are not fully resectable, resulting in recurrence, malignant progression, and eventual death. Approximately 69–80% of grade II and III gliomas harbor mutations in the isocitrate dehydrogenase 1 gene (IDH1), of which 83–90% are found to be the IDH1-R132H mutation. Detection of the IDH1-R132H mutation should help in the differential diagnosis of grade II and III gliomas from other types of CNS tumors and help determine the boundary between the tumor and normal brain tissue. In this study, we established a highly sensitive antibody-based device, referred to as the immuno-wall, to detect the IDH1-R132H mutation in gliomas. The immuno-wall causes an immunoreaction in microchannels fabricated using a photo-polymerizing polymer. This microdevice enables the analysis of the IDH1 status with a small sample within 15 min with substantially high sensitivity. Our results suggested that 10% content of the IDH1-R132H mutation in a sample of 0.33 μl volume, with 500 ng protein, or from 500 cells is theoretically sufficient for the analysis. The immuno-wall device will enable the rapid and highly sensitive detection of the IDH1-R132H mutation in routine clinical practice.     

Plasma CVD of (BaSr)TiO3 Dielectrics for Gigabit DRAM Capacitors

Electron cyclotron resonance (ECR) plasma chemical vapor deposition (CVD) of (BaSr)TiO₃ dielectrics is reviewed. The oxygen plasma lowered the crystallization temperature and carbon contamination. (BaSr)TiO₃ CVD process was developed under conditions of relatively low deposition rate of 1.1 nm/min and a relatively low deposition temperature of 550°C. Utilizing this process, we developed a gigabit dynamic random access memory (DRAM) capacitor technology involving the preparation of a thin (BaSr)TiO₃ capacitor dielectric over a RuO₂/Ru storage node contacting a TiN/TiSi _X /poly-Si plug. The ECR plasma CVD enabled uniform deposition of gigabit-DRAM-quality (BaSr)TiO₃ films on the electrode sidewalls. The storage node contact improved in endurance against oxidation, by fabricating the buried-in TiN/TiSi _X plug (TiN-capped plug) under the RuO₂/Ru storage node. (BaSr)TiO₃ films with a small equivalent SiO₂ thickness of 0.38 nm and a leakage current density of 8.5×10^–7 A/cm² at an applied voltage of 1.0 V, were obtained without any further annealing process. An equivalent SiO₂ thickness of 0.40 nm on the RuO₂ sidewall was also achieved. It is concluded that this technology has reached the requirements for gigabit DRAM capacitors.     

Impact of time dependent dielectric breakdown and stress-inducedleakage current on the reliability of high dielectric constant(Ba,Sr)TiO3 thin-film capacitors for Gbit-scale DRAMs

Time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) are investigated for the reliability of (Ba,Sr)TiO₃ (BST) thin films. Both time to breakdown (T_BD) versus electric field (E) and T_BD versus 1/E plots show universal straight lines, independent of the film thickness, and predict lifetimes longer than 10 y at +1 V for 50 nm BST films with an SiO₂ equivalent thickness of 0.70 nm. SILC is observed at +1 V after electrical stress of BST films; nevertheless, 10 y reliable operation for Gbit-scale DRAMs is predicted in spite of charge loss by SILC. Lower (Ba+Sr)/Ti ratio is found to be strongly beneficial for low leakage, low SILC, long TBD, and therefore greater long-term reliability. This suggests a worthwhile tradeoff against the dielectric constant, which peaks at a (Ba+Sr)/Ti ratio of 1.05     

Barrier mechanism of Pt/Ta and Pt/Ti layers for SrTiO3 thin film capacitors on Si

Abstract

The barrier effect of Pt/Ta and Pt/Ti has been investigated, when used as bottom electrodes for SrTiO₃ thin film capacitors on Si. The Pt/Ta/Si stacks were more stable than the Pt/Ti/Si, both in vacuum and in oxygen annealing. Though the Pt/Ta bilayer was suitable for the SrTiO₃ deposition at 400[ddot]C, its resistivity became slightly higher after the deposition at 600[ddot]C, due to Ta layer oxidation during the SrTiO₃ deposition. This would result in a contact resistance problem for high density dynamic random access memory application.     

A stacked capacitor technology with ECR plasma MOCVD(Ba,Sr)TiO3 and RuO2/Ru/TiN/TiSixstorage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO₃ thin films is described, The four-layer RuO₂/Ru/TiN/TiSi_x, storage node configuration allows 500°C processing and fine-patterning down to the 0.20 μm size by electron beam lithography and reactive ion etching. Good insulating (Ba_0.4Sr_0.6)TiO₃ (BST) films with an SiO₂ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1×10^{-/6 A}cm² at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 μm size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 μm² with only the 0.3 μm high-storage electrodes