An Enhanced Low Noise Amplifier Circuit at 6 GHz Center Frequency and NF Improvement in 180 nm CMOS Process

Wireless Personal Communications - This paper presents the design and simulation of a modified CMOS low noise amplifier (LNA) circuit in 180 nm CMOS standard technology. We modified a...     

A 110–140 GHz Millimeter-Wave VCO Using Varactor and Bulk Effective Technique in 65 nm CMOS Process

In this paper, an enhanced voltage controlled oscillator (VCO) at center frequency 125 GHz with tuning rang of 24% is presented. The proposed idea is based on the tuning capacitance using MOS varactor. The structure is consisted of applying an MOS varactor capacitor to the drain and bulk (in parallel) of NMOS transistor in 65 nm CMOS standard technology. The obtained output of the proposed VCO at 2nd harmonic is tunable at 110–140 GHz frequency with applying?±?1.2 input tuning voltage. Simulation results of the proposed circuit are obtained after extracting post layout (with total chip size of 0.07 mm²) and confirm theoretical results. Compared to the resent designs, the obtained results indicate that the proposed circuit has high tuning range, low die area and a good figure of merit @ 1.2 power supply voltage.

     

A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz) by applying?±?1.2 V input voltage variation. The divide-by-4 ILFD circuit uses a cross coupled VCO with three injection transistors acting in linear and nonlinear regions. The frequency dividers such as divided-by-4 ILFD, subsequent current mode logic (CML) and true single phase clock (TSPC) as divider chain with ratio 1/256 are used to synthesize frequency 244 MHz which is compared to reference frequency, 244 MHz in the PLL. Simulation results of the proposed PLL circuit are obtained after extracting post layout (with total chip size of 0.29 mm²) in 65 nm CMOS standard technology and @ 1.2 V power supply voltage. The obtained results confirm theoretical relations and indicate that the proposed circuit has good figure of merit (FoM), and higher tuning range and lower die area than the recent designs.