排序方式: 共有157条查询结果,搜索用时 15 毫秒
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传统异构FPGA工艺映射算法一般不打破实现专用功能和查找表功能的子网表之间的层次边界,因而缩小了映射的优化空间.为此提出一种利用区域重组打破单元间层次边界的异构FPGA工艺映射算法.首先利用贪心策略实现FPGA多单元的映射,即优先使用性能好的专用功能单元;然后利用标记锥实现子网表之间的区域重组,打破专用功能单元和查找表之间的层次边界,减小了映射结果的面积和延迟开销.实验结果表明,与公认的ABC中的工艺映射算法相比,该算法能平均减少逻辑单元面积12.2%,减少电路关键路径延时2.5%. 相似文献
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生化微传感集成系统是目前的研究焦点,本文以在线性区和饱和区两种模式下工作的pH-ISFET作为研究对象,提出ISFET微传感器与其信号读出电路的单芯片集成,并深入研究传感机理以及与标准CMOS兼容的敏感材料制备技术.整个芯片包含ISFET/REFET微传感差分对、双模式ISFET/REFET放大器、次级差分放大、参比电极Pt、恒流源等,采用新加坡Chartered半导体集成电路公司3.3V标准CMOS工艺流片.同时进行传感器芯片的pH响应实验测试,获得53mV/pH灵敏度. 相似文献
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测试配置开发是FPGA测试中的重要环节之一,为加快FPGA测试配置开发进程,提出一种基于配置词典的FPGA测试配置分析评价方法.首先建立FPGA基本可编程单元的配置词典,给出其完备测试需要的所有配置码;然后采用模板化的方法分析测试配置,计算测试配置对配置词典的覆盖率;最后根据计算的覆盖率评价测试配置的完备性.实验结果表明,文中方法能够正确地评价测试配置的完备程度,报告测试配置所有可测和不可测的FPGA资源;与故障仿真方法相比,该方法的时间复杂度从O(kpn2)减少到O(kn′),运行时间从数百小时缩短到几分钟,且运行时间独立于FPGA的阵列规模. 相似文献
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This paper presents a CMOS G_m-C complex filter for a low-IF receiver of the IEEE802.15.4 standard.A pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator.A detailed analysis of non-ideality of the OTA and the frequency tuning method is elaborated.The analysis and measurement results have shown that the center frequency of the complex filter could be tuned accurately.The chip was fabricated in a standard 0.35μm CMOS process,with a single 3.3 V power supply.The filter consumes 2.1 mA current,has a measured in-band group delay ripple of less than 0.16μs and an IRR larger than 28 dB at 2 MHz apart,which could meet the requirements of the IEEE802.15.4 standard. 相似文献
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This paper proposes a novel technique for modeling the electrostatic discharge (ESD) characteristic of the enclosed-gate layout transistors (ELTs). The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELF is decomposed into edge and comer transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM (Berkeley Short- channel IGFET Model). Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification. 相似文献
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本篇文章提出了基于采用高度灵活的互连盒的互连网络的一种新型的现场可编程模拟阵列(FPAA)结构,该结构可以在双模式下工作包括离散时间模式和连续时间模式,以追求在不同应用场合下的性能要求。高度灵活的互连盒中的开关不仅用来作为可编程开关还直接作为开关电容中电荷转移的开关来使用,大大减少了离散时间模式下信号路径上的开关,提高了整体电路的性能。该款FPAA采用0.18um CMOS工艺,3.3V电源电压。后仿结果显示互连网络的最大带宽可达265MHz, 从示例的测试结果可以看出该款FPAA在连续时间模式下可工作在2MHz信号带宽下,无杂散动态范围可达54dB, 离散时间工作模式下的处理精度可达96.4%。 相似文献
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This paper proposes an area-saving dual-path loop filter(LPF)for low-voltage integrated phase-locked loops(PLLs).With this LPF,output current of the lowpass-path charge-pump(CP)is B times(B〉1)as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW. 相似文献