CMOS low-power bandpass IF filter for Bluetooth

Design of a CMOS 18th-order IF (intermediate frequency) bandpass filter for integrated low-IF Bluetooth receivers is presented. The centre frequency and bandwidth of the filter are 3 and 1 MHz, respectively. The proposed filter is based on unity gain fully differential voltage buffers and provides efficient, low power and a small area design solution. The filter, including its automatic tuning circuit, occupies an area of 0.6 mm² in a standard 0.5 mum-CMOS chip. Experimental results show that the filter satisfies the selectivity and dynamic range requirements of Bluetooth while operating from a total supply current of 0.9 mA     

A CMOS highly linear channel-select filter for 3G multistandardintegrated wireless receivers

A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm² in a 0.5-μm chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54), 89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA     

A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.     

CMOS digitally programmable quadrature oscillators

CMOS digitally programmable quadrature oscillators based on digitally controlled current followers and voltage followers are proposed. The proposed designs provide the advantage of programmability similar to the operational transconductance amplifier‐based oscillators while offering improved linearity. In mixed analog/digital systems, the digital tuning feature allows direct interfacing with the digital signal processing part. Novel realizations that provide both voltage‐mode and current‐mode quadrature sinusoidal signals are presented. Employing only grounded capacitors the designs achieve independent control of the frequency and condition of oscillation that can be tuned digitally. Experimental results obtained from a 0.35 µm CMOS chip fabricated using standard CMOS process are given. Copyright © 2008 John Wiley & Sons, Ltd.     

A CMOS multi-gain transconductance amplifier and its applications

Transconductance amplifier (g_m) based circuits are attractive due to their inherent programmability features. Single output g_m’s are often replaced by multi-output g_m’s to reduce the number of active devices for a given application. However, this usually results in losing the circuit programmability features. This work shows that this problem can be circumvented through adopting a new programmable multi-gain g_m. The advantages of the proposed multi-gain g_m are demonstrated using two filter design examples. They show that the proposed multi-gain g_m reduces the number of active devices by two-third compared with their single output g_m based counterparts while maintaining their versatile programmability characteristics. Experimental results obtained from a 0.18 μm CMOS process for one of the applications are provided.     

CMOS baseband filter for WCDMA integrated wireless receivers

A new second-order lowpass filter based on a single CMOS fully differential current conveyor is presented. Developed from the Sallen-Key highpass filter, the proposed filter is AC coupled and provides programmable gain. Moreover, the filter exhibits low noise, high linearity and low power, making it suitable for implementing the baseband filter of a WCDMA direct-conversion wireless receiver. A WCDMA filter having a programmable bandwidth around 2.1 MHz, a variable gain range of 50 dB and a DC notch below 2 kHz using passive components below 5 kW for resistors and 20 pF for capacitors is implemented. Experimental and simulation results obtained from fabricated chips are included     

CMOS highly linear fully differential current conveyor

Design of a CMOS robust low-distortion fully differential second-generation current conveyor (CCII) is presented. The proposed circuit is essential to extend the use of the CCII-based circuits to high-performance VLSI applications. The design avoids using current mirror(s) in the signal path in order to minimise the distortion caused by mismatched mirroring transistors. The proposed circuit is implemented in a standard 0.5 /spl mu/m CMOS technology and its different characteristics are measured. Statistical measurement results show that the proposed fully differential CCII exhibits total harmonic distortion (THD) of -78.9 dB associated with less than 0.1 dB variation.     

Implementation of reconfigurable nth-order filter based on CCII

Topologies for realizing voltage and current mode reconfigurable nth-order filters based on the second-generation current conveyor (CCII) are assessed. The most compatible structure for field-programmable analog array is identified. A CCII adopting active current division networks are utilized for implementing the proposed filter leading to wide control of its coefficients. Programmability characteristics are demonstrated through experimental results obtained from integrated circuit chips fabricated in a 0.18 μm CMOS process.     

Universal three input and one output current-mode filter withoutexternal passive elements

A new current-mode universal filter is proposed. The filter uses only operational amplifiers and operational transconductance amplifiers (OTAs) and can realise lowpass, highpass, bandpass, notch and allpass responses without changing circuit topology. The parameters ω₀, ω₀/Q₀, and the gain can be electronically tuned by adjusting the bias currents of the OTAs. The proposed circuit has low sensitivity     

A compact digitally programmable reconfigurable filter for dual-mode BT/802.11b receivers

A new 4th-order reconfigurable (complex bandpass or normal lowpass) filter for implementing the channel select filter for dual-mode receivers adopting low-IF for Bluetooth (BT) and zero-IF for WLAN (IEEE 802.11b) is presented. It provides an alternative solution to the optimum low-power complex filter based on the current amplifier. The new filter avoids the employment of capacitor and/or resistor banks leading to an area efficient design solution while maintaining high linearity and relatively low power consumption. The center frequency in BT mode and the pole frequency in 802.11b mode are digitally tuned through programming active current division networks (CDNs). Experimental results obtained from 0.18 μm CMOS chips show that the proposed design offers improved characteristics over available solutions in terms of power consumption, spurious-free dynamic range (SFDR) and/or area. It achieves in-band SFDR of 65.3 dB for BT and 65.2 dB for 802.11b while it consumes 1.8 mW. Also, it offers image rejection of better than 59 dB.