Sintering studies of nano-crystalline zinc oxide

Sintering and grain growth of nano-crystalline undoped ZnO has been studied in detail over a wide range of temperature and holding time. Below 800 °C, sintering of over 70% theoretical density is not observed, irrespective of particle size. At 900 °C for 6 h, the nano-crystalline sample sinters to 99% of theoretical density whereas the density for as received sample is 93% of theoretical density. However, at 1300 °C or higher, the densification is found to be much faster and after a few hours becomes independent of holding time. Grain growth studies reveal a similar feature of attaining saturation over holding time. The average saturated grain size is found to be ∼1.5 and ∼2.2 μm at 800 and 900 °C, respectively, while at 1300 °C or higher, it is in between 12 and 13 μm.     

A Critical Grain Size Concept to Predict the Impact Transition Temperature of Ti-Microalloyed Steels

Based on the assumption that local principal stress remains the same everywhere within a ferrite grain, a critical value of grain size can be determined for a fixed TiN particle size. When the grain size is smaller than the critical size, grain boundary is expected to resist the propagation of a micro-crack that is initiated from a TiN particle. Using this concept, an attempt has been made to predict the local cleavage fracture stress and 27J impact transition temperature (ITT) of different Ti-microalloyed steels, which were subjected to (instrumented) Charpy impact testing.     

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.     

Outage and BER analysis of cellular CDMA for integrated services with correlated signal and interference

In this letter, we evaluate the outage and "minimum duration outage" probabilities for integrated services in cellular code-division multiple-acess systems considering correlation among signal and interferers. Correlation is found to lower the outage probability. The effect of correlation and power control error on bit error rate is also studied.     

Hole mobility enhancement in strained-Si p-MOSFETs under high vertical field

The growth of a high quality, step-graded lattice-relaxed SiGe buffer layer on a Si(100) substrate is investigated. p-MOSFETs were fabricated on strained-Si grown on top of the above layer. Carrier confinement at the type-II strained-Si/SiGe buffer interface is observed clearly from the device transconductance and C-V measurements. At high vertical field, compared to bulk silicon, the channel mobility of the strained-Si device with x=0.18 is found to be about 40% and 200% higher at 300 K and 77 K respectively. Measurements on transconductance enhancement are also reported. Data at 77 K provide evidence of two channels and a large enhancement of mobility at high transverse field.     

A low power scheduling scheme with resources operating at multiplevoltages

This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n²) algorithm and 2) a high complexity O(n² log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%     

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Applications based on Discrete Fourier Transforms (DFT) are extensively used in several areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation- and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application specific and reconfigurable hardware have utilized this scheme for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex-5 devices. For a 2K ×2K input size, the proposed architecture is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.     

Construction and generation of OCDMA code families using a complete row-wise orthogonal pairs algorithm

A new code construction algorithm for incoherent Multi-Dimensional Optical Code Division Multiple Access (MD-OCDMA) for asynchronous fiber optic communication is proposed. We refer multi-dimensionality to two-dimensional (2D) wavelength–time or space–time domains and three-dimensional (3D) space–wavelength–time domains. The application of the algorithm in constructing 2D multiple pulses per row codes and 3D multiple pulses per plane codes is given. The performance of the codes is discussed. In the applications discussed, this construction ensures a maximum crosscorrelation of 1 between any two codes. The proposed codes have complete 1D code allocation, which increases the cardinality. The performance of some codes in literature is compared with the proposed codes. The analyzed performance measure is bit error rate due to multiple access interference for different numbers of active users. The performance analysis shows that the proposed 2D construction offers very low bit error rate at lower spectral efficiency when compared with other 2D constructions. A comparison of the proposed 3D construction with existing 3D constructions shows lower bit error rate for equivalent code dimension. New integrated optic designs for the generation of OCDMA codes using titanium indiffused lithium niobate technology are explored, which can enable compact encoders and decoders for computer communications.     

Electronic states of organic semiconductors vis-à-vis interactions between molecules in a submonolayer through time-restricted electrostatic assembly

We have made in-depth studies to revisit time-restricted layer-by-layer (LbL) electrostatic assembly process of a couple of organic molecules. The studies have been made in relation to electronic states of metal phthalocyanines. We show that by shortening dipping time for adsorption of the active molecules, mass adsorbed in each monolayer can be decreased and hence intermolecular spacing between the molecules can be increased. We have characterized the (sub)monolayers deposited on an electrode with scanning tunneling microscope tip to record tunneling current through the molecules. Results show that the highest occupied molecular orbitals and lowest unoccupied molecular orbitals, and also the difference between the orbitals, that is, the transport gap of the molecules in a (sub)monolayer depends on the dipping time of LbL assembly or molecule-to-molecule separation. We show that interactions between molecules in a monolayer decrease the transport gap of the metal phthalocyanines.