On the FinFET extension implant energy

The need of an ultrashallow junction technology for the extension of p-FinFETs has been investigated by integrated process and device simulations. For devices with 60 nm physical gate length, whose extensions are activated in a low thermal-budget process (spike anneal), it is found that the I/sub off/-I/sub on/ performance is invariant with respect to the extension implant energy. Nevertheless, the short-channel behavior worsens. This can be remedied by adding spacers to both sides of the gate before the extension implant, resulting in virtually identical dc characteristics and speed. Devices with gate lengths of 18 nm and below require dopant activation with negligible diffusion. Under those circumstances the short channel behavior of the FinFET is limited by the lateral straggle of the ion implant. Spacers may remedy what is otherwise poor short channel behavior due to a relatively high energy extension implant. However, this comes at the price of drastically worse drive current at a fixed off-current.     

Transient-enhanced diffusion in shallow-junction formation

Shallow junctions are formed in crystalline Si by low-energy ion implantation of B⁺, P⁺, or As⁺ species accompanied by electrical activation of dopants by rapid thermal annealing and the special case of spike annealing. Diffusion depths were determined by secondary ion-mass spectroscopy (SIMS). Electrical activation was characterized by sheet resistance, Hall coefficient, and reverse-bias diode-leakage measurements. The B⁺ and P⁺ species exhibit transient-enhanced diffusion (TED) caused by transient excess populations of Si interstitials. The electrically activated fraction of implanted dopants depends mainly on the temperature for B⁺ species, while for P⁺ species, it depends on both temperature and P⁺ dose. The relatively small amount of diffusion associated with As⁺ implants is favorable for shallow-junction formation with spike annealing.     

Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.     

Ultra-shallow junction formation by spike annealing in a lamp-based or hot-walled rapid thermal annealing system: effect of ramp-up rate

Ultra-shallow p-type junction formation has been investigated using 1050°C spike anneals in lamp-based and hot-walled rapid thermal processing (RTP) systems. A spike anneal may be characterized by a fast ramp-up to temperature with only a fraction of a second soak-time at temperature. The effects of the ramp-up rate during a spike anneal on junction depth and sheet resistance were measured for rates of 40, 70 and 155°C/s in a lamp-based RTP, and for 50 and 85°C/s in a hot-walled RTP. B⁺ implants of 0.5, 2 and 5 keV at doses of 2×10¹⁴ and 2×10¹⁵ cm⁻² were annealed. A significant reduction in junction depth was observed at the highest ramp-up rate for the shallower 0.5-keV B implants, while only a marginal improvement was observed for 2- and 5-keV implants. It is concluded that high ramp-up rates can achieve the desired ultra-shallow junctions with low sheet resistance but only when used in combination with spike anneals and the lowest energy implants.     

Reduction of carrier depletion in p/sup +/ polysilicon gates using laser thermal processing

A novel laser thermal processing (LTP) technique was used to fabricate p/sup +/-gated MOS capacitors with ultrathin gate oxides. It is found that the introduction of LTP prior to the gate activation anneal increases the carrier concentration at the poly-Si gate/gate oxide interface substantially, as compared to rapid thermal anneal (RTA) alone. Thus, LTP readily reduces the poly-depletion effect in p/sup +/-poly-Si gates. This is achieved without observable gate oxide degradation or boron penetration. Secondary ion mass spectrometry analyzes show that the boron concentration near the gate/gate oxide interface increases significantly after the post-LTP anneal. A possible mechanism for this increase in carrier concentration is the diffusion of boron atoms toward the gate oxide by a complex process known as explosive crystallization.     

The staging of rectal tumors with endorectal study technics: the demonstration of a possible source of error

HLA-DRB1 is the most polymorphic gene described so far, and their encoded molecules disclose a major role in allogeneic responses. We describe in this report a new DRB1 allele in a Spanish Caucasian bone marrow donor, initially defined by PCR-SSO as a DRB1*11-like allele. Complete exon 2 cDNA-sequencing reveled that this allele was identical to DRB1*1119 except for a single substitution at position 178, which generates an amino acid change (Tyr-His) at position 60. This residue is shared by several DRB1*14 subtypes and DRB1*0808. The new allele was officially named DRB1*1131.     

Radiation damage induced by 5 keV Si ion implantation in strained-Si/Si0.8Ge0.2

The damage distributions induced by ultra low energy ion implantation (5 keV Si⁺) in both strained-Si/Si_0.8Ge_0.2 and normal Si are measured using high-resolution RBS/channeling with a depth resolution better than 1 nm. Ion implantation was performed at room temperature over the fluence range from 2 × 10¹³ to 1 × 10¹⁵ ions/cm². Our HRBS results show that the radiation damage induced in the strained Si is slightly larger than that in the normal Si at fluences from 1 × 10¹⁴ to 4 × 10¹⁴ ions/cm² while the amorphous width is almost the same in both strained and normal Si.