Estimating and reducing the memory requirements of signal processing codes for embedded systems

Most embedded systems have limited amount of memory. In contrast, the memory requirements of the digital signal processing (DSP) and video processing codes (in nested loops, in particular) running on embedded systems is significant. This paper addresses the problem of estimating and reducing the amount of memory needed for transfers of data in embedded systems. First, the problem of estimating the region associated with a statement or the set of elements referenced by a statement during the execution of nested loops is analyzed. For a fixed execution ordering, a quantitative analysis of the number of elements referenced is presented; exact expressions for uniformly generated references and a close upper and lower bound for nonuniformly generated references are derived. Second, in addition to presenting an algorithm that computes the total memory required, this paper also discusses the effect of transformations (that change the execution ordering) on the lifetimes of array variables, i.e., the time between the first and last accesses to a given array location. The term maximum window size is introduced, and quantitative expressions are derived to compute the maximum window size. A detailed analysis of the effect of unimodular transformations on data locality, including the calculation of the maximum window size, is presented.     

Multidimensional vector radix FHT algorithms

In this paper, efficient multidimensional (M-D) vector radix (VR) decimation-in-frequency and decimation-in-time fast Hartley transform (FHT) algorithms are derived for computing the discrete Hartley transform (DHT) of any dimension using an appropriate index mapping and the Kronecker product. The proposed algorithms are more effective and highly suitable for hardware and software implementations compared to all existing M-D FHT algorithms that are derived for the computation of the DHT of any dimension. The butterflies of the proposed algorithms are based on simple closed-form expressions that allow easy implementations of these algorithms for any dimension. In addition, the proposed algorithms possess properties such as high regularity, simplicity and in-place computation that are highly desirable for software and hardware implementations, especially for the M-D applications. A close relationship between the M-D VR complex-valued fast Fourier transform algorithms and the proposed M-D VR FHT algorithms is established. This type of relationship is of great significance for software and hardware implementations of the algorithms, since it is shown that because of this relationship and the fact that the DHT is an alternative to the discrete Fourier transform (DFT) for real data, a single module with a little or no modification can be used to carry out the forward and inverse M-D DFTs for real- or complex-valued data and M-D DHTs. Thus, the same module (with a little or no modification) can be used to cover all domains of applications that involve the DFTs or DHTs.     

On the VLSI implementation of real-time order statistic filters

Real-time implementation of an order-statistic filter (OSF) or ranked order filter requires the computation of the order statistic (ranked order) of the samples in a window which gets periodically updated with the arrival of a new sample(s). The authors give an algorithm for the computation of the running order statistic. A highly parallel architecture suitable for VLSI implementation is presented. The architecture is very versatile, with programmable window size and rank order. An expansion algorithm and its VLSI architecture, which permit the usage of two r-bit OSFs to implement an (r+1)-bit OSF, where r is the resolution of the input signal samples, are given. In a special case where one is satisfied with at most one LSB error, the hardware complexity of the proposed architecture can be reduced by almost one half. It is further shown how a VLSI chip incorporating the proposed architecture can be used as the basic building block in the real-time implementation of other forms of nonlinear filters     

Wavelet domain-based video noise reduction using temporal discrete cosine transform and hierarchically adapted thresholding

A novel spatio-temporal filter for video denoising, which operates entirely in the wavelet domain, is proposed. For effective noise reduction, the spatial and temporal redundancies that exist in the wavelet domain representation of a video signal are exploited. First, a 2D discrete wavelet transform is applied to the input noisy frames. This is followed by a discrete cosine transform (DCT), which is applied to the temporal subband coefficients to minimise the redundancy among the consecutive frames. The DCT transformed, noise-free coefficients in the different wavelet domain subbands for the original image sequence are modelled using a prior having a generalised Gaussian distribution. On the basis of this prior, filtering of the noisy wavelet coefficients in each subband is carried out using a new, low-complexity wavelet shrinkage method, which utilises the correlation that exists between subsequent resolution levels. Experimental results show that the proposed scheme outperforms several state-of-the-art spatio-temporal filters in terms of both the peak signal-to-noise ratio and the visual quality     

Microstructural development in microsecond pulsed laser melted polycrystalline nickel

The microsecond Nd glass pulsed laser interaction with polycrystalline nickel was studied with particular emphasis on melting and the nature of the microstructural development following irradiation. The change in the melt pool shape and the melting efficiency as a function of the total laser power has been determined. Evidence is presented to show that for low energy pulse, the microstructural development accompanies fresh nucleation of grains and leads to a finer grain size than that of the substrate. At a higher energy level, growth competition leads to a coarser grain size. We also report a banded feature roughly parallel to the melt substrate interface that develops in the resolidified region during high energy interaction. These results are discussed in the light of our present understanding of rapid solidification processes.